公开(公告)号：US20060017675A1

公开(公告)日：2006-01-26

申请号：US11187953

申请日：2005-07-25

申请人： Fumikazu Shimoshikiryoh

发明人： Fumikazu Shimoshikiryoh

IPC分类号： G09G3/36

CPC分类号： G09G3/3655 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2300/0876 ,  G09G2310/06 ,  G09G2320/0223 ,  G09G2320/028

摘要： In a liquid crystal display device performing multi-picture element driving, gate OFF timing of a switching element connected between each sub picture element and a signal line is matched with phase timing when all the subsidiary capacity wires are at the same potential. This prevents the occurrence of uneven luminance appearing in a lateral streak.

公开(公告)号：US09196206B2

公开(公告)日：2015-11-24

申请号：US12451074

申请日：2008-04-22

申请人： Masae Kitayama ,  Fumikazu Shimoshikiryoh ,  Kentaroh Irie ,  Toshihide Tsubata ,  Naoshi Yamada ,  Hidetoshi Nakagawa

发明人： Masae Kitayama ,  Fumikazu Shimoshikiryoh ,  Kentaroh Irie ,  Toshihide Tsubata ,  Naoshi Yamada ,  Hidetoshi Nakagawa

IPC分类号： G09G3/36 ,  G02F1/1337 ,  G02F1/1362

CPC分类号： G09G3/3677 ,  G02F1/133707 ,  G02F1/134336 ,  G02F1/1362 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/122 ,  G02F2201/123 ,  G09G3/2077 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3666 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2300/0876 ,  G09G2310/0224 ,  G09G2310/0286 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2320/0233 ,  G11C19/00

摘要： In one embodiment of the present invention, each pixel includes first and second subpixels. CS bus lines connected to the respective storage capacitors of the first and second subpixels are electrically independent of each other. A CS voltage has a waveform that inverts its polarity at least once a frame, which includes a first subframe for sequentially scanning a series of odd rows and a second SF for sequentially scanning even rows that have been skipped during the first SF. A source signal voltage varies so as to have two frames or subframes with mutually opposite polarities. A CS voltage has a waveform that has quite opposite consequences on the effective voltage of a subpixel of a pixel connected to the jth scan line to be selected during the first subframe and on that of another subpixel of a pixel connected to the (j+1)th scan line to be selected during the second subframe. In this manner, the deterioration in display quality, which would be caused if either a source line inversion drive or a block inversion drive is applied to a multi-pixel technology, can be minimized.

摘要翻译： 在本发明的一个实施例中，每个像素包括第一和第二子像素。 连接到第一和第二子像素的各个存储电容器的CS总线彼此电独立。 CS电压具有至少一帧反转其极性的波形，其包括用于顺序扫描一系列奇数行的第一子帧和用于顺序扫描在第一SF期间被跳过的偶数行的第二SF。 源极信号电压发生变化，从而具有相互极性相反的两个帧或子帧。 CS电压具有与第一子帧期间要选择的第j扫描线连接的像素的子像素的有效电压和连接到第（j + 1）像素的像素的另一子像素的有效电压具有相反的结果的波形 ）扫描线在第二子帧期间被选择。 以这种方式，如果将源极线反转驱动或块反转驱动应用于多像素技术，则会导致显示质量的劣化。

公开(公告)号：US08872744B2

公开(公告)日：2014-10-28

申请号：US13263424

申请日：2010-02-09

申请人： Masae Kitayama ,  Fumikazu Shimoshikiryoh ,  Kentaroh Irie

发明人： Masae Kitayama ,  Fumikazu Shimoshikiryoh ,  Kentaroh Irie

IPC分类号： G09G3/36 ,  G02F1/1362 ,  G09G5/00

CPC分类号： G09G3/3614 ,  G02F1/136286 ,  G09G3/3659 ,  G09G3/3674 ,  G09G3/3685 ,  G09G5/006 ,  G09G2300/0426 ,  G09G2300/0447 ,  G09G2300/0876 ,  G09G2310/0205 ,  G09G2310/067 ,  G09G2320/0219 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/08 ,  H04N5/7408

摘要： In at least one embodiment a ripple, generated in an electric potential of data signal lines even in long-term reversal driving, is reduced and display quality is improved. In at least one example embodiment, the liquid crystal display apparatus of the present invention includes scanning signal lines and data signal lines, in which one scanning pulse is outputted to select one scanning signal line, each of the data signal lines receives data signals whose polarities are reversed per one vertical scanning period while in one horizontal scanning period, one of two data signal lines receives a data signal having a polarity and the other of the two data signal lines receives another data signal having another polarity, the two data signal lines being arranged adjacent to each other, scanning pulses are successively outputted in sets of two, and at a timing in which two scanning pulses fall, two scanning pulses rise.

摘要翻译： 在至少一个实施例中，即使在长期反转驱动中也在数据信号线的电位中产生的纹波被减小并且显示质量得到改善。 在至少一个示例性实施例中，本发明的液晶显示装置包括扫描信号线和数据信号线，其中输出一个扫描脉冲以选择一条扫描信号线，每条数据信号线接收极性的数据信号 在一个垂直扫描周期中反转，而在一个水平扫描周期中，两条数据信号线之一接收具有极性的数据信号，另外两条数据信号线中的另一条数据信号线接收到另一极性的另一数据信号，两条数据信号线为 相邻配置的扫描脉冲依次输出为两组，在两个扫描脉冲下降的定时，两个扫描脉冲上升。

公开(公告)号：US08830152B2

公开(公告)日：2014-09-09

申请号：US13581056

申请日：2011-02-24

申请人： Fumikazu Shimoshikiryoh

发明人： Fumikazu Shimoshikiryoh

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3655 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2300/0876 ,  G09G2320/028

摘要： A liquid crystal display device (100A) according to the present invention includes a pixel (10) including first and second subpixels (10a, 10b) and a first CS bus line (24a), which is associated with the first subpixel. The first subpixel includes a liquid crystal capacitor (13a) and a first storage capacitor (22a). The second subpixel includes a liquid crystal capacitor (13b). A first CS signal voltage applied to the first storage capacitor (22a) through the first CS bus line (24a) is an oscillation voltage, of which one period is shorter than one vertical scanning period, and has first and second potentials that define a maximum amplitude and a third potential between the first and second potentials. When a gate signal voltage Vg supplied to the gate bus line (12) that has been high goes low, the first CS signal voltage Vcsa supplied to its associated first CS bus line (24a) is at the third potential.

摘要翻译： 根据本发明的液晶显示装置（100A）包括与第一子像素相关联的包括第一和第二子像素（10a，10b）和第一CS总线（24a）的像素（10）。 第一子像素包括液晶电容器（13a）和第一存储电容器（22a）。 第二子像素包括液晶电容器（13b）。 通过第一CS总线（24a）施加到第一存储电容器（22a）的第一CS信号电压是一个周期短于一个垂直扫描周期的振荡电压，并且具有限定最大值的第一和第二电位 幅度和第一和第二电位之间的第三电位。 当提供给已经很高的栅极总线（12）的栅极信号电压Vg变低时，提供给其相关联的第一CS总线（24a）的第一CS信号电压Vcsa处于第三电位。

公开(公告)号：US20140146265A1

公开(公告)日：2014-05-29

申请号：US14235875

申请日：2012-07-26

申请人： Masahiko Nakamizo ,  Fumikazu Shimoshikiryoh ,  Takamitsu Suzuki ,  Akifumi Hashimoto

发明人： Masahiko Nakamizo ,  Fumikazu Shimoshikiryoh ,  Takamitsu Suzuki ,  Akifumi Hashimoto

IPC分类号： G02F1/133

CPC分类号： G02F1/13306 ,  G02F1/136213 ,  G02F2001/134345 ,  G09G3/3655 ,  G09G2300/0443 ,  G09G2300/0876 ,  G09G2310/06 ,  G09G2330/021

摘要： In a liquid crystal display device in which one pixel is divided into a plurality of sub-pixels, power consumption is reduced. A liquid crystal display device in which a pixel formation portion forming one pixel includes a first sub-pixel portion and a second sub-pixel portion is provided with a charge sharing circuit (50) for short-circuiting a CS bus line (CSL1) provided for the first sub-pixel portion and a CS bus line (CSL2) provided for the second sub-pixel portion to each other based on a short-circuit control signal (CTL). A CS voltage generating circuit (40) generates CS signals (CS1 and CS2) whose potentials change every predetermined period. The charge sharing circuit (50) short-circuits the CS bus line (CSL1) and the CS bus line (CSL2) to each other at timing at which the potentials of the CS signals (CS1 and CS2) change, based on the short-circuit control signal (CTL).

摘要翻译： 在其中一个像素被划分为多个子像素的液晶显示装置中，功耗降低。 其中形成一个像素的像素形成部分包括第一子像素部分和第二子像素部分的液晶显示装置设置有用于短路CS总线（CSL1）的电荷共享电路（50），所述CS总线 基于短路控制信号（CTL），对于第一子像素部分和为第二子像素部分提供的CS总线（CSL2）。 CS电压产生电路（40）产生其电位在每个预定周期改变的CS信号（CS1和CS2）。 在CS信号（CS1和CS2）的电位变化的定时，电荷共享电路（50）使CS总线（CSL1）和CS总线（CSL2）彼此短路， 电路控制信号（CTL）。

公开(公告)号：US08665199B2

公开(公告)日：2014-03-04

申请号：US13855368

申请日：2013-04-02

申请人： Masae Kitayama ,  Kentaro Irie ,  Fumikazu Shimoshikiryoh ,  Toshihide Tsubata ,  Naoshi Yamada

发明人： Masae Kitayama ,  Kentaro Irie ,  Fumikazu Shimoshikiryoh ,  Toshihide Tsubata ,  Naoshi Yamada

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3655 ,  G09G3/3677 ,  G09G2300/0443 ,  G09G2300/0876 ,  G09G2310/0205 ,  G09G2310/0224 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0261 ,  G09G2320/028

摘要： A gate driver creates a dummy insertion period in which the driver does not apply a gate on pulse to a scanning signal line immediately after the time of the inversion of a data signal. When a period from the time of the application of the gate on pulse to an odd numbered or even numbered scanning signal line to which the gate on pulse is applied previously to the time of the application of the gate on pulse to an even numbered or odd numbered scanning signal line to which the gate on pulse is applied later is set as an adjacent line writing time lag period for two scanning signal lines adjacent to each other, a CS control circuit allows the polarity of every CS signal to be reversed on the same cycle at least in the adjacent line writing time lag period.

摘要翻译： 门驱动器创建虚拟插入周期，其中驱动器在数据信号的反转时间之后立即将扫描信号线施加脉冲的栅极。 当从施加栅极导通脉冲的时间到预先施加栅极导通脉冲的奇数或偶数扫描信号线的时间到施加栅极导通脉冲的时间到偶数或奇数 将稍后施加栅极导通脉冲的编号扫描信号线设置为彼此相邻的两个扫描信号线的相邻线写入时间延迟时段，CS控制电路允许每个CS信号的极性相同 至少在相邻行写周期中循环。

公开(公告)号：US20130321384A1

公开(公告)日：2013-12-05

申请号：US13985539

申请日：2012-02-10

申请人： Toshikazu Tsuchiya ,  Masae Kitayama ,  Fumikazu Shimoshikiryoh

发明人： Toshikazu Tsuchiya ,  Masae Kitayama ,  Fumikazu Shimoshikiryoh

IPC分类号： G09G5/00

CPC分类号： G09G5/001 ,  G09G3/3648 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2320/0209

摘要： A display device includes first and second display pixels connected to a first source line, third and fourth display pixels connected to the second source line. The device further includes a receiver receiving display voltage for each display pixel, a calculator calculating first difference voltage between the display voltages of the first and second display pixels, and calculating a second difference voltage between the display voltages of the third and fourth display pixels. A parasitic capacitance is generated between the first display pixel and each source line and between the third display pixel and each source line. The display device further includes a generator correcting the first display voltage based on the first and second difference voltages and generating first write voltage for the first display pixel, and correcting the third display voltage based on the second difference voltage and generating third write voltage for the third display pixel.

摘要翻译： 显示装置包括连接到第一源极线的第一和第二显示像素，连接到第二源极线的第三和第四显示像素。 该装置还包括接收器，用于接收每个显示像素的显示电压，计算器计算第一和第二显示像素的显示电压之间的第一差分电压，并计算第三和第四显示像素的显示电压之间的第二差值电压。 在第一显示像素和每个源极线之间以及第三显示像素和每个源极线之间产生寄生电容。 显示装置还包括发生器，其基于第一和第二差分电压校正第一显示电压并产生第一显示像素的第一写入电压，并且基于第二差分电压校正第三显示电压并产生第三写入电压， 第三显示像素。

公开(公告)号：US20130207884A1

公开(公告)日：2013-08-15

申请号：US13880384

申请日：2011-10-26

申请人： Masahiko Nakamizo ,  Fumikazu Shimoshikiryoh ,  Takamitsu Suzuki ,  Akifumi Hashimoto

发明人： Masahiko Nakamizo ,  Fumikazu Shimoshikiryoh ,  Takamitsu Suzuki ,  Akifumi Hashimoto

IPC分类号： G09G5/10

CPC分类号： G09G5/10 ,  G09G3/3659 ,  G09G2320/0233

摘要： A display device 10 according to the present invention includes a plurality of pixels 40 each including a plurality of sub pixels 42, a plurality of auxiliary capacitance lines 36 forming an auxiliary capacitance 56 with the sub pixels 42, and an auxiliary capacitance driver 34 configured to supply an auxiliary capacitance drive signal to the auxiliary capacitance lines 36 and to apply a voltage to the auxiliary capacitance. In the display device 10, the auxiliary capacitance driver 34 includes a plurality of connection terminals 64 each connected to each of the auxiliary capacitance lines 36.

摘要翻译： 根据本发明的显示装置10包括多个像素40，每个像素包括多个子像素42，多个辅助电容线36，其形成具有子像素42的辅助电容56，辅助电容驱动器34被配置为 向辅助电容线36提供辅助电容驱动信号，并向辅助电容施加电压。 在显示装置10中，辅助电容驱动器34包括各自连接到每个辅助电容线36的多个连接端子64。

公开(公告)号：US08427413B2

公开(公告)日：2013-04-23

申请号：US12451957

申请日：2008-03-27

申请人： Masae Kitayama ,  Kentaro Irie ,  Fumikazu Shimoshikiryoh ,  Toshihide Tsubata ,  Naoshi Yamada

发明人： Masae Kitayama ,  Kentaro Irie ,  Fumikazu Shimoshikiryoh ,  Toshihide Tsubata ,  Naoshi Yamada

IPC分类号： G09G3/36

CPC分类号： G09G3/36 ,  G02F1/13624 ,  G02F2001/133397 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0443 ,  G09G2300/0876 ,  G09G2310/0205 ,  G09G2310/0224 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0233 ,  G09G2320/0261 ,  G09G2320/028

摘要： In one embodiment of the present invention, a liquid crystal display device is disclosed in which a gate driver applies a gate-on pulse so that a second period is longer than a first period. The first period and the second period are defined as follows. Among gate-on pulses applied before the moment of polarity inversion of a data signal, the last end of the gate-on pulse nearest to the moment of the polarity inversion is earlier than the end time of the horizontal period during which the gate-on pulse is applied. The first period starts at the last end of the gate-on pulse and ends at the end time of the horizontal period during which the gate-on pulse is applied. The second period starts at the moment of the polarity inversion and ends at the moment of the application start of the gate-on pulse nearest to the moment of the polarity inversion among the gate-on pulses applied after the polarity inversion. Thus, even when a data signal waveform is not sharp upon polarity inversion, it is possible to suppress display unevenness and perform a high-quality display.

摘要翻译： 在本发明的一个实施例中，公开了一种液晶显示装置，其中栅极驱动器施加栅极导通脉冲，使得第二周期比第一周期长。 第一期和第二期定义如下。 在数据信号极性反转之前施加的栅极导通脉冲中，最接近极性反转时刻的栅极导通脉冲的最后一端早于栅极导通的水平周期的结束时间 脉冲被施加。 第一个周期从栅极导通脉冲的最后一个开始，并在施加栅极导通脉冲的水平周期的结束时间结束。 第二周期从极性反转开始，在极性反转后施加的栅极导通脉冲之间的最接近极性反转的时刻的栅极导通脉冲的施加开始时刻结束。 因此，即使当极性反转时数据信号波形不尖锐时，也可以抑制显示不均匀并进行高质量的显示。

公开(公告)号：US20130002992A1

公开(公告)日：2013-01-03

申请号：US13575696

申请日：2011-01-27

申请人： Mitsuaki Hirata ,  Masae Kitayama ,  Kenichi Hyohdoh ,  Ikumi Itsumi ,  Yuki Yamashita ,  Akane Sugisaka ,  Fumikazu Shimoshikiryoh

发明人： Mitsuaki Hirata ,  Masae Kitayama ,  Kenichi Hyohdoh ,  Ikumi Itsumi ,  Yuki Yamashita ,  Akane Sugisaka ,  Fumikazu Shimoshikiryoh

IPC分类号： G02F1/1333

CPC分类号： G09G3/207 ,  G02F1/1362 ,  G02F2201/52 ,  G09G3/2074 ,  G09G3/2077 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3655 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2300/0452 ,  G09G2300/0876 ,  G09G2310/0262 ,  G09G2320/0673 ,  G09G2320/068

摘要： A liquid crystal display device (100) according to the present invention includes a color display pixel D including pixels PA through PD arrayed in a matrix. The pixels PA through PD respectively include sub pixels SA1 through SD1 and sub pixels SA2 through SD2. At least at an intermediate gray scale level, the luminance of the sub pixels SA2 through SD2 is higher than the luminance of the sub pixels SA1 through SD1. The plurality of sub pixels S included in the pixels PA through PD are arrayed in a matrix. The sub pixel SA2 is adjacent to the sub pixel SB2 in the row direction, is adjacent to the sub pixel SC2 in the column direction, and is adjacent to the sub pixel SD2 in an oblique direction.

摘要翻译： 根据本发明的液晶显示装置（100）包括包括以矩阵排列的像素PA至PD的彩色显示像素D。 像素PA至PD分别包括子像素SA1至SD1和子像素SA2至SD2。 至少在中间灰度级，子像素SA2至SD2的亮度高于子像素SA1至SD1的亮度。 包括在像素PA至PD中的多个子像素S被排列成矩阵。 子像素SA2在行方向上与子像素SB2相邻，在列方向上与子像素SC2相邻，并且与倾斜方向上的子像素SD2相邻。