公开(公告)号：US10056373B2

公开(公告)日：2018-08-21

申请号：US15490702

申请日：2017-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L29/94 ,  H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

公开(公告)号：US09960256B2

公开(公告)日：2018-05-01

申请号：US14282089

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L21/44 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L29/66795 ,  H01L21/76804 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66 ,  H01L29/785

Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

公开(公告)号：US09905473B1

公开(公告)日：2018-02-27

申请号：US15598447

申请日：2017-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Vimal Kamineni ,  Michael Aquilino

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545

Abstract: A method of fabricating a FinFET device includes a self-aligned contact etch where a source/drain contact module is performed prior to a replacement metal gate (RMG) module. In particular, the method involves forming a sacrificial gate over the channel region of a fin, and an interlayer dielectric over adjacent source/drain regions of the fin. An etch mask is then used to protect source/drain contact regions and enable the removal of the interlayer dielectric from outside of the protected area, e.g., between adjacent fins. A sacrificial cobalt layer is used to backfill the cavities formed by etching the interlayer dielectric prior to forming a functional gate.

公开(公告)号：US20170330834A1

公开(公告)日：2017-11-16

申请号：US15154367

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Keith H. Tabakman ,  Patrick D. Carpenter ,  Guillaume Bouche ,  Michael V. Aquilino

IPC: H01L23/535 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.

公开(公告)号：US09818640B1

公开(公告)日：2017-11-14

申请号：US15271475

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  Guillaume Bouche

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L23/528

Abstract: A method includes providing a structure having a first hardmask layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer. A gamma trench is patterned into the second hardmask layer and between the mandrels. Self-aligned inner spacers are formed on sidewalls of the gamma trench, the inner spacers forming a portion of a pattern. The pattern is etched into the dielectric stack to form an array of alternating mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in a perpendicular X direction. The portion of the pattern formed by the inner spacers is utilized to form a pair of non-mandrel line cuts in a non-mandrel line. The non-mandrel line cuts are self-aligned in the Y direction.

公开(公告)号：US09812396B1

公开(公告)日：2017-11-07

申请号：US15175495

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  Guillaume Bouche ,  Shreesh Narasimha ,  Patrick Ryan Justison ,  Byoung Youp Kim ,  Craig Michael Child, Jr.

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L23/5286 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283

Abstract: A method includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a first metallization layer with a first power rail. The method further includes forming a second metallization layer over the first metallization layer with a second power rail, and directly electrically connecting the first power rail and the second power rail, the directly electrically connecting including forming metal-filled vias between the first power rail and the second power rail. The method further includes forming additional metallization layer(s) over the second metallization layer with additional power rail(s), and directly electrically connecting each of the additional power rail(s) to a power rail of a metallization layer directly below.

公开(公告)号：US09793169B1

公开(公告)日：2017-10-17

申请号：US15175187

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huy Cao ,  Huang Liu ,  Guillaume Bouche ,  Songkram Srivathanakul

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/823431 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3115 ,  H01L29/66795

Abstract: One method disclosed herein includes, among other things, forming a process layer on a substrate, forming a carbon-containing silicon dioxide layer above the process layer and forming a patterned mask layer above the carbon-containing silicon dioxide layer. The patterned mask layer exposes portions of the carbon-containing silicon dioxide layer. A material modification process is performed on the exposed portions of the carbon-containing silicon dioxide layer to generate modified portions, and the modified portions are removed. The process layer is etched using remaining portions of the carbon-containing silicon dioxide layer as an etch mask.

公开(公告)号：US09691775B1

公开(公告)日：2017-06-27

申请号：US15141087

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent Licausi ,  Eric Scott Kozarsky ,  Guillaume Bouche

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/1104 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/0924

Abstract: A semiconductor cell includes a substrate and an array of at least five substantially parallel fins having substantially equal fin widths disposed on the substrate. The array includes a predetermined minimum spacing distance between at least one pair of adjacent fins within the array. The array has a first n-type fin for an n-type semiconductor device, and a first p-type fin for a p-type semiconductor device. The first p-type fin is disposed adjacent the first n-type fin and spaced a predetermined first n-to-p distance apart from the first n-type fin. The first n-to-p distance is greater than the minimum spacing distance and less than the sum of the fin width plus twice the minimum spacing distance.

公开(公告)号：US09660040B2

公开(公告)日：2017-05-23

申请号：US14926657

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L29/94 ,  H01L29/417 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

公开(公告)号：US20170047247A1

公开(公告)日：2017-02-16

申请号：US15336589

申请日：2016-10-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Mark A. Zaleski

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density.

Abstract translation: 本发明的实施例提供了一种在线结构的后端中自对准金属切割的方法。 牺牲Mx + 1线形成在金属Mx线之上。 每个Mx + 1牺牲线上形成间隔。 使用间隔件之间的间隙来确定切割到Mx金属线的位置和厚度。 这样可确保Mx金属线切割不会侵入连接Mx和Mx + 1电平的通孔。 它还允许通过外壳规则降低限制，从而增加电路密度。