公开(公告)号：US09153693B2

公开(公告)日：2015-10-06

申请号：US13917019

申请日：2013-06-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hong Yu ,  Wang Zheng ,  Huang Liu ,  Yongsik Moon

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/785 ,  H01L21/28008 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795

Abstract: An intermediate semiconductor structure of a FinFET device in fabrication includes a substrate, a plurality of fin structures coupled to the substrate and a dummy gate disposed perpendicularly over the fin structures. A portion of the dummy gate is removed between the fin structures to create one or more vias and the one or more vias are filled with a dielectric. The dummy gate is then replaced with a metal gate formed around the dielectric-filled vias.

Abstract translation: 在制造中的FinFET器件的中间半导体结构包括衬底，耦合到衬底的多个翅片结构和垂直于翅片结构设置的虚拟栅极。 在翅片结构之间去除虚拟栅极的一部分以产生一个或多个通孔，并且一个或多个通孔用电介质填充。 然后用在电介质填充的通孔周围形成的金属栅极替换虚拟栅极。

公开(公告)号：US08940650B2

公开(公告)日：2015-01-27

申请号：US13787521

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC: H01L21/31 ,  H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/0217

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。

公开(公告)号：US08859417B2

公开(公告)日：2014-10-14

申请号：US13733282

申请日：2013-01-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jialin Yu ,  Huang Liu ,  Jilin Xia

IPC: H01L21/4763 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L21/28088 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/485 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductive structure(s), such as a gate electrode(s) or a contact structure(s), and methods of fabrication thereof are provided. The conductive structure(s) includes a first conductive layer of a first conductive material, and a second conductive layer of a second conductive material. The second conductive layer is disposed over the first conductive layer, and at least a portion of the first conductive material includes grains having a size larger than a defined value, and at least a second portion of the second conductive material includes grains having a size less than the defined value. In one embodiment, the first and second conductive materials are the same conductive material, with different-sized grains.

Abstract translation: 提供导电结构，例如栅电极或接触结构，以及其制造方法。 导电结构包括第一导电材料的第一导电层和第二导电材料的第二导电层。 第二导电层设置在第一导电层上，并且第一导电材料的至少一部分包括尺寸大于限定值的晶粒，并且第二导电材料的至少第二部分包括尺寸较小的晶粒 比定义的值。 在一个实施例中，第一和第二导电材料是相同的导电材料，具有不同尺寸的晶粒。

公开(公告)号：US20140256141A1

公开(公告)日：2014-09-11

申请号：US13787521

申请日：2013-03-06

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Huy Cao ,  Huang Liu ,  Hoong Shing Wong ,  Songkram Srivathanakul ,  Sandeep Gaan

IPC: H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/0217

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供包括设置在其上的半导体器件的半导体衬底，并且使用第一沉积工艺在半导体衬底之上和半导体器件上沉积第一氮化硅层。 第一沉积工艺是在多个循环中操作的等离子体增强化学气相沉积（PECVD）工艺，每个循环具有第一时间间隔和第二时间间隔。 PECVD方法包括以下步骤：在第一时间间隔期间产生具有电源的等离子体，等离子体包括提供硅的气体和提供供给气体的反应性离子和自由基物质，并且在第二时间期间停止产生等离子体 间隔紧随着第一个时间间隔。 该方法还包括在多个循环之后在第一氮化硅层上沉积第二氮化硅层。

公开(公告)号：US20140227858A1

公开(公告)日：2014-08-14

申请号：US13765723

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US08803254B2

公开(公告)日：2014-08-12

申请号：US13687355

申请日：2012-11-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jean-Baptiste Laloe ,  Huang Liu ,  Wonwoo Kim

IPC: H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third metal layer comprised of titanium aluminum (TiAl) positioned above the second metal layer, a fourth metal layer comprised of an aluminum-containing material positioned above the third metal layer, a fifth metal layer comprised of titanium positioned above the fourth metal layer, and a layer of aluminum positioned above the fifth metal layer.

Abstract translation: 一种用于NFET器件的说明性栅极结构包括形成在半导体衬底上的栅极绝缘层，由位于栅极绝缘层上方的氮化钛（TiN）构成的第一金属层，由位于上部的氮化钽（TaN）组成的第二金属层 所述第一金属层，由位于所述第二金属层上方的钛铝（TiAl）构成的第三金属层，由位于所述第三金属层上方的含铝材料构成的第四金属层，由位于所述第三金属层上方的钛构成的第五金属层 第四金属层和位于第五金属层上方的铝层。

公开(公告)号：US20140145274A1

公开(公告)日：2014-05-29

申请号：US13687355

申请日：2012-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jean-Baptiste Laloe ,  Huang Liu ,  Wonwoo Kim

IPC: H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823821 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: One illustrative gate structure for an NFET device includes a gate insulation layer formed above a semiconducting substrate, a first metal layer comprised of titanium nitride (TiN) positioned above the gate insulation layer, a second metal layer comprised of tantalum nitride (TaN) positioned above the first metal layer, a third metal layer comprised of titanium aluminum (TiAl) positioned above the second metal layer, a fourth metal layer comprised of an aluminum-containing material positioned above the third metal layer, a fifth metal layer comprised of titanium positioned above the fourth metal layer, and a layer of aluminum positioned above the fifth metal layer.

Abstract translation: 一种用于NFET器件的说明性栅极结构包括形成在半导体衬底上的栅极绝缘层，由位于栅极绝缘层上方的氮化钛（TiN）构成的第一金属层，由位于上部的氮化钽（TaN）组成的第二金属层 所述第一金属层，由位于所述第二金属层上方的钛铝（TiAl）构成的第三金属层，由位于所述第三金属层上方的含铝材料构成的第四金属层，由位于所述第三金属层上方的钛构成的第五金属层 第四金属层和位于第五金属层上方的铝层。