公开(公告)号：US20090230462A1

公开(公告)日：2009-09-17

申请号：US12393509

申请日：2009-02-26

申请人： Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/11582

摘要： Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.

摘要翻译： 每个存储器串包括：在垂直方向上延伸到衬底的第一柱状半导体层; 多个第一导电层，其形成为夹着具有电荷陷阱层的绝缘层并以二维方式扩展; 第二柱状半导体层，其与所述第一柱状半导体层的顶表面接触并且在垂直方向上延伸到所述衬底; 以及多个第二导电层，其形成为与第二柱状半导体层夹着绝缘层，并且形成为沿与垂直方向正交的第一方向延伸的条纹图案。 多个第一导电层的第一方向的端部相对于彼此分步地形成，多个第二导电层的整体形成在第一导电层的顶层的正上方的区域中， 并且多个第一导电层和多个第二导电层被与多个第一导电层和第二导电层连续形成的保护绝缘层覆盖。

公开(公告)号：US20090224309A1

公开(公告)日：2009-09-10

申请号：US12389977

申请日：2009-02-20

申请人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Masaru Kidoh ,  Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/792 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so that the semiconductor layer infills the first hole and the second hole after the removal of the sacrificing layer

摘要翻译： 一种制造非易失性半导体存储装置的方法，包括：形成第一导电层，使其通过第一绝缘层沿上下方向夹持; 形成第一孔，使其穿透第一绝缘层和第一导电层; 在面向所述第一孔的侧壁上形成第一侧壁绝缘层; 形成牺牲层，使牺牲层填充第一孔; 在牺牲层的上层上形成第二导电层，使得第二导电层在上下方向上被第二绝缘层夹持; 在与所述第一孔匹配的位置上形成第二孔，使得所述第二孔穿过所述第二绝缘层和所述第二导电层; 在面向所述第二孔的侧壁上形成第二侧壁绝缘层; 在形成第二侧壁绝缘层之后去除牺牲层; 以及形成半导体层，使得半导体层在去除牺牲层之后填充第一孔和第二孔

公开(公告)号：US07539056B2

公开(公告)日：2009-05-26

申请号：US11896261

申请日：2007-08-30

申请人： Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Mitsuru Sato

发明人： Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Mitsuru Sato

IPC分类号： G11C16/04

CPC分类号： G11C16/24 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： In a NAND type flash memory, control electrodes of first select transistors in a plurality memory cell units extending along a data line is integrated to constitute a first select signal line while control electrodes of second select transistor are integrated to constitute a second select signal line. The second select signal line is displaced from the first select signal line by a half pitch.

摘要翻译： 在NAND型闪速存储器中，集成了沿着数据线延伸的多个存储单元单元中的第一选择晶体管的控制电极，以构成第一选择信号线，同时第二选择晶体管的控制电极被积分以构成第二选择信号线 。 第二选择信号线从第一选择信号线移位半个间距。

公开(公告)号：US20090101969A1

公开(公告)日：2009-04-23

申请号：US12248577

申请日：2008-10-09

申请人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

发明人： Ryota KATSUMATA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi ,  Yasuyuki Matsuoka

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator, and serving as the one of the source and the drain while being in contact with the first conductive layer; a channel which is buried in the gate opening above the second conductive layer so as to face the gate electrode film with the gate insulator therebetween, and which has a channel layer generated therein, the channel layer allowing majority carriers to flow between the source and the drain in response to a voltage applied to the gate; and a third conductive layer buried in the gate opening above the channel so as to be in contact with the gate insulator to serve as the other one of the source and the drain.

摘要翻译： 一种半导体器件，包括：半导体衬底; 设置在所述基板的表面上并用作源极和漏极之一的第一导电层; 设置在所述第一导电层上的第一绝缘膜; 设置在所述第一绝缘膜上的栅电极膜; 设置在栅电极膜上的第二绝缘膜; 设置为穿透第二绝缘膜的栅极开口，栅极电极膜和第一绝缘膜，以暴露第一导电层的一部分; 设置在所述第一导电层的位于所述栅极开口正下方的表面中的凹部; 栅极绝缘体，其设置在所述栅极开口的侧表面上，并且在所述第一绝缘膜和所述凹部之间的部分处具有突出形状; 第二导电层，其被埋置在所述凹部中并且位于所述栅极开口的底部以与所述栅极绝缘体接触，并且在与所述第一导电层接触的同时用作所述源极和漏极中的一个; 埋入在第二导电层上方的栅极开口中以与门极绝缘体相对的栅极电极膜并且其中产生沟道层的沟道，该沟道层允许多数载流子在源极和源极之间流动 响应于施加到门的电压而漏极; 以及掩埋在沟道上方的栅极开口中的第三导电层，以便与栅极绝缘体接触以用作源极和漏极中的另一个。

公开(公告)号：US20080180994A1

公开(公告)日：2008-07-31

申请号：US11955900

申请日：2007-12-13

申请人： Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Masaru Kito ,  Hideaki Aochi ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

发明人： Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Masaru Kito ,  Hideaki Aochi ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka

IPC分类号： G11C11/34 ,  H01L29/76 ,  G11C8/00

CPC分类号： H01L27/115 ,  G11C7/18 ,  G11C8/08 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.

摘要翻译： 半导体存储器件具有半导体衬底，形成在所述半导体衬底的表面上的第一选择晶体管，形成在所述第一选择晶体管上方的第一虚拟晶体管，形成在所述第一虚拟晶体管上方的多个存储单元晶体管， 垂直于所述半导体衬底的表面，每个所述存储单元晶体管包括具有电荷累积功能的绝缘层，形成在所述存储单元晶体管上方的第二虚拟晶体管以及形成在所述第二虚设晶体管上方的第二选择晶体管; 其中第一电位被提供给所述第一选择晶体管的栅电极和所述第一虚拟晶体管的栅电极，并且第二电位被提供给所述第二选择晶体管的栅极和所述第二虚设晶体管的栅电极 写入操作的时间将数据写入到所述存储单元晶体管。

公开(公告)号：US20070252201A1

公开(公告)日：2007-11-01

申请号：US11654551

申请日：2007-01-18

申请人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

发明人： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC分类号： H01L29/76

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

摘要翻译： 提供了具有新结构的非易失性半导体存储器件，其中以三维状态层叠存储单元，从而可以减小芯片面积。 本发明的非易失性半导体存储装置是具有串联连接有多个电可编程存储单元的多个存储串的非易失性半导体存储装置。 存储器串包括柱形半导体; 形成在柱状半导体周围的第一绝缘膜; 形成在所述第一绝缘膜周围的电荷存储层; 形成在电荷存储层周围的第二绝缘膜; 并且形成在第二绝缘膜周围的第一或第n电极（n是大于1的自然数）。 存储器串的第一或第n电极和存储器串的其它第一或第n电极分别是以二维状态扩展的第一或第n导体层。

公开(公告)号：US07276750B2

公开(公告)日：2007-10-02

申请号：US10922228

申请日：2004-08-20

申请人： Masaru Kito ,  Masaru Kido ,  Hideaki Aochi ,  Toshiharu Tanaka ,  Ryota Katsumata ,  Hideki Inokuma ,  Yoichi Takegawa

发明人： Masaru Kito ,  Masaru Kido ,  Hideaki Aochi ,  Toshiharu Tanaka ,  Ryota Katsumata ,  Hideki Inokuma ,  Yoichi Takegawa

IPC分类号： H01L27/08 ,  H01L31/00 ,  H01L29/76 ,  H01L29/06

CPC分类号： H01L27/10867 ,  H01L29/945 ,  Y10S257/906

摘要： A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench and electrically connected to a storage electrode of the capacitor; a select transistor provided on a surface of the semiconductor substrate and having a source region in contact with the trench; a spacer covering a side of the source region; and a surface strap contact arranged upon the spacers, the source region and the storage node.

摘要翻译： 半导体器件包括具有沟槽的半导体衬底; 电容器 环状氧化膜，布置在电容器上方的沟槽的一侧的一部分上; 存储节点，其布置在所述沟槽的上部中的所述环状氧化物膜的一侧，并且电连接到所述电容器的存储电极; 设置在所述半导体衬底的表面上并具有与所述沟槽接触的源极区域的选择晶体管; 覆盖源区一侧的间隔物; 以及布置在间隔件，源区域和存储节点上的表面带接触件。

公开(公告)号：US07135368B2

公开(公告)日：2006-11-14

申请号：US11044896

申请日：2005-01-27

申请人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi

发明人： Masaru Kito ,  Ryota Katsumata ,  Hideaki Aochi

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A method of fabricating a semiconductor memory device, comprising recess-etching a major surface of a semiconductor substrate, thereby forming a pillar that becomes a device formation region; burying an insulation film in the recess-etched region, thereby forming a device isolation region; burying a first oxide film at a side wall of the pillar on the device isolation region; forming a second oxide film on an upper part of the pillar; and removing an upper part of the first oxide film using the second oxide film as a mask, thereby exposing an upper surface and an upper part of the side wall of the pillar; and the method, comprising forming a conductive material on the exposed upper surface and the exposed upper part of the side wall of the pillar, thereby forming a surface strap that electrically connects the capacitor and the second activation region.

摘要翻译： 一种制造半导体存储器件的方法，包括凹入蚀刻半导体衬底的主表面，从而形成成为器件形成区域的柱; 在凹陷蚀刻区域中埋设绝缘膜，由此形成器件隔离区域; 在器件隔离区域上的柱的侧壁上埋设第一氧化物膜; 在柱的上部形成第二氧化膜; 并使用第二氧化膜作为掩模去除第一氧化物膜的上部，从而暴露柱的侧壁的上表面和上部; 该方法包括在暴露的上表面和柱的侧壁的暴露的上部形成导电材料，从而形成电连接电容器和第二激活区域的表面带。

公开(公告)号：US20050145914A1

公开(公告)日：2005-07-07

申请号：US10892496

申请日：2004-07-16

申请人： Toshiharu Tanaka ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kido

发明人： Toshiharu Tanaka ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kido

IPC分类号： H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/20 ,  H01L29/76

CPC分类号： H01L27/10867 ,  H01L29/66181 ,  H01L29/945

摘要： A semiconductor memory includes a semiconductor substrate; a capacitor arranged in a lower portion of the trench; a collar oxide film arranged on a side of the trench above the capacitor and having an upper collar member and a lower collar member, the upper collar member being thinner than the lower collar member so as to provide a height difference therebetween; a storage node arranged on a side of the collar oxide film; a select transistor provided on the semiconductor substrate and having a doped layer in contact with the collar oxide film; and a conductor portion arranged upon the storage node and the doped layer.

摘要翻译： 半导体存储器包括半导体衬底; 布置在沟槽的下部的电容器; 环形氧化膜，布置在电容器上方的沟槽的一侧，并具有上衣领构件和下衣领构件，上衣领构件比下衣领构件更薄，以便在它们之间提供高度差; 布置在所述轴环氧化膜侧的存储节点; 设置在半导体衬底上并具有与环氧化膜接触的掺杂层的选择晶体管; 以及布置在存储节点和掺杂层上的导体部分。

公开(公告)号：US20050127424A1

公开(公告)日：2005-06-16

申请号：US10806398

申请日：2004-03-23

申请人： Masaru Kito ,  Hideaki Aochi

发明人： Masaru Kito ,  Hideaki Aochi

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/10829

摘要： A semiconductor memory device includes an element region and an element-isolating region provided on a semiconductor substrate, a capacitor formed in a trench, a first insulating film formed on a side surface of the trench on the capacitor, a first conductive layer provided on the first insulating film and the capacitor so as to bury the trench, a second insulating film provided on a side surface of the trench and on the first insulating film and on both side surfaces of the element region, a gate electrode provided on the element region through a gate insulating film, a source region and a drain region provided in the element region, and a contact layer provided on the first conductive layer and the element region to connect the first conductive layer with the source region or the drain region.

摘要翻译： 半导体存储器件包括元件区域和设置在半导体衬底上的元件隔离区域，形成在沟槽中的电容器，形成在电容器上的沟槽的侧表面上的第一绝缘膜，设置在电容器上的第一导电层 第一绝缘膜和电容器，以埋入沟槽;第二绝缘膜，设置在沟槽的侧表面上，在第一绝缘膜上以及元件区域的两个侧表面上;栅电极，设置在元件区域上，通过 栅极绝缘膜，设置在元件区域中的源极区域和漏极区域，以及设置在第一导电层和元件区域上以将第一导电层与源极区域或漏极区域连接的接触层。