公开(公告)号：US20210399119A1

公开(公告)日：2021-12-23

申请号：US16910008

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Suresh VISHWANATH ,  Roza KOTLYAR ,  Han Wui THEN ,  Robert EHLERT ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Sandrine CHARUE-BAKKER

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L21/285 ,  H01L29/66

Abstract: Embodiments disclosed herein comprise a high electron mobility transistor (HEMT). In an embodiment, the HEMT comprises a heterojunction channel that includes a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. In an embodiment a first interface layer is between the first semiconductor layer and the second semiconductor layer, and a second interface layer is over the first interface layer. In an embodiment, the HEMT further comprises a source contact, a drain contact, and a gate contact between the source contact and the drain contact.

公开(公告)号：US20200266278A1

公开(公告)日：2020-08-20

申请号：US16279150

申请日：2019-02-19

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Paul B. FISCHER ,  Walid M. HAFEZ

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H01L21/765 ,  H01L21/28 ,  H01L29/66 ,  H01L23/66

Abstract: A semiconductor device structure having a “T-shaped” gate structure is described. A narrower first portion supports high frequency processes (e.g., gigahertz wireless communications). A second portion of the gate structure has a second width greater than the first width. Lateral extensions (sometimes referred to as “field plates), thinner and wider than the second portion, extend from the second portion. This combination of a gate structure having a narrow first portion and a wider second portion improves the performance of the semiconductor device in applications that involve both high frequency and high power consumption.

公开(公告)号：US20200227545A1

公开(公告)日：2020-07-16

申请号：US16651327

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Stephan LEUSCHNER ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/765 ,  H01L21/285 ,  H01L29/66 ,  H03F3/45 ,  H03F3/21

Abstract: Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.

公开(公告)号：US20200227544A1

公开(公告)日：2020-07-16

申请号：US16651326

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Stephan LEUSCHNER ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/765 ,  H01L21/285 ,  H01L29/66 ,  H03F3/21 ,  H03F3/45

Abstract: Gallium nitride (GaN) transistors with drain field plates and their methods of fabrication are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, and a drain field plate above the drain region, wherein the drain field plate is not electrically coupled to the gate structure or the source region.

公开(公告)号：US20200066889A1

公开(公告)日：2020-02-27

申请号：US16321411

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/40

Abstract: Embodiments of the invention include a semiconductor device and methods of forming such devices. In an embodiment, the semiconductor device includes a source region, a drain region, and a channel region formed between the source region and drain region. In an embodiment, a first interlayer dielectric (ILD) may be formed over the channel region, and a first opening is formed through the first ILD. In an embodiment, a second ILD may be formed over the first ILD, and a second opening is formed through the second ILD. Embodiments of the invention include the second opening being offset from the first opening. Embodiments may also include a gate electrode formed through the first opening and the second opening. In an embodiment, the offset between the first opening and the second opening results in the formation of a field plate and a spacer that reduces a gate length of the semiconductor device.

公开(公告)号：US20190355843A1

公开(公告)日：2019-11-21

申请号：US16475220

申请日：2017-02-02

Applicant: INTEL CORPORATION

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H04B1/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/762

Abstract: An apparatus, an integrated circuit die, and a method of fabricating a group III-nitride (III-N) integrated RF front-end circuit are disclosed. The apparatus includes a III-N integrated radio frequency (RF) front-end circuit that includes a semiconductor substrate, a plurality of functional blocks, each of the plurality of functional blocks comprising a III-N structure on the semiconductor substrate. The III-N integrated RF front-end circuit is to be coupled to an antenna.

公开(公告)号：US20190252511A1

公开(公告)日：2019-08-15

申请号：US15772783

申请日：2015-12-09

Applicant: Intel Corporation

Inventor： Scott B. CLENDENNING ,  Han Wui THEN ,  John J. PLOMBON ,  Michael L. MCSWINEY

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L29/4966 ,  C23C16/30 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L27/0886

Abstract: Embodiments of the present disclosure describe semiconductor devices with ruthenium phosphorus thin films and further describe the processes to deposit the thin films. The thin films may be deposited in a gate stack of a transistor device or in an interconnect structure. The processes to deposit the films may include chemical vapor deposition and may include ruthenium precursors. The precursors may contain phosphorus. A co-reactant may be used during deposition. A co-reactant may include a phosphorus based compound. A gate material may be deposited on the film in a gate stack. The ruthenium phosphorus film may be a metal diffusion barrier and an adhesion layer, and the film may be a work function metal for some embodiments. Other embodiments may be described and/or claimed.

公开(公告)号：US20190189611A1

公开(公告)日：2019-06-20

申请号：US16322082

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L27/02 ,  H01L29/20 ,  H01L29/778 ,  H01L29/861 ,  H01L29/417 ,  H01L29/205 ,  H01L29/167 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8258 ,  H01L29/08 ,  C23C16/30 ,  C23C16/04

CPC classification number: H01L27/0255 ,  C23C16/042 ,  C23C16/303 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/0332 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/8258 ,  H01L27/0248 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/36 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/66136 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/8611

Abstract: A semiconductor structure including a group III-N semiconductor material is disposed on a silicon substrate. A group III-N transistor structure is disposed on the group III-N semiconductor material. A well is disposed in the silicon substrate. The well has a first conductivity type. A doped region is disposed in the well. The doped region has a second conductivity type that is opposite to the first conductivity type. A first electrode is connected to the well of the second conductivity type and a second electrode is connected to the doped region having a first conductivity type. The well and the doped region form a PN diode. The well or the doped region is connected to the raised drain structure of the group III-N transistor.

公开(公告)号：US20180350921A1

公开(公告)日：2018-12-06

申请号：US15771985

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY

IPC: H01L29/267 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/778 ,  H01L21/02

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02516 ,  H01L21/02568 ,  H01L21/02609 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/78681

Abstract: Described herein are methods and structures integrating one or more TMDC crystal heteroepitaxially grown on one or more group III-Nitride (III-N) crystal. The TMDC crystal may be grown on a III-N heteroepitaxial crystal that has been grown on crystalline silicon substrate. One or more of III-N devices and silicon devices employing separated regions of the heteroepitaxial substrate may be integrated with a TMDC device fabricated on with the TMDC crystal. In some embodiments, impurity-doped III-N source/drain regions provide a low resistance coupling between metallization and a TMDC-channeled transistor.

公开(公告)号：US20180331191A1

公开(公告)日：2018-11-15

申请号：US15777140

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/765

CPC classification number: H01L29/404 ,  H01L21/765 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: Embodiments of the invention include a high voltage transistor with one or more field plates and methods of forming such transistors. According to an embodiment, the transistor may include a source region, a drain region, and a gate electrode formed over a channel region formed between the source region and drain region. Embodiments of the invention may also include a first interlayer dielectric (ILD) formed over the channel region and a second ILD formed over the first ILD. According to an embodiment, a first field plate may be formed in the second ILD. In an embodiment the first field plate is not formed as a single bulk conductive feature with the gate electrode. In some embodiments, the first field plate may be electrically coupled to the gate electrode by one or more vias. In alternative embodiments, the first field plate may be electrically isolated from the gate electrode.