公开(公告)号：US20220199519A1

公开(公告)日：2022-06-23

申请号：US17129854

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Chia-Ching LIN ,  Sou-Chi CHANG ,  Kaan OGUZ ,  I-Cheng TUNG ,  Arnab SEN GUPTA ,  Ian A. YOUNG ,  Uygar E. AVCI ,  Matthew V. METZ ,  Ashish Verma PENUMATCHA ,  Anandi ROY

IPC: H01L23/522 ,  H01L49/02

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. The first capacitor dielectric is or includes a perovskite high-k dielectric material. A second electrode plate is on the first capacitor dielectric and has a portion over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and has a portion over and parallel with the second electrode plate.

公开(公告)号：US20220102521A1

公开(公告)日：2022-03-31

申请号：US17033471

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Nazila HARATIPOUR ,  Siddharth CHOUKSEY ,  Jack T. KAVALIEROS ,  Jitendra Kumar JHA ,  Matthew V. METZ ,  Mengcheng LU ,  Anand S. MURTHY ,  Koustav GANGULY ,  Ryan KEECH ,  Glenn A. GLASS ,  Arnab SEN GUPTA

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

公开(公告)号：US20220028972A1

公开(公告)日：2022-01-27

申请号：US17493695

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Nicholas G. MINUTILLO ,  Sean T. MA ,  Anand S. MURTHY ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Gilbert DEWEY

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20210265482A1

公开(公告)日：2021-08-26

申请号：US17239439

申请日：2021-04-23

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

公开(公告)号：US20210057413A1

公开(公告)日：2021-02-25

申请号：US16954126

申请日：2018-03-28

Applicant: Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Intel Corporation

Inventor： Gilbert DEWEY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS ,  Aaron D. LILAK ,  Willy RACHMADY ,  Rishabh MEHANDRU ,  Kimin JUN ,  Anh PHAN ,  Hui Jae YOO ,  Patrick MORROW ,  Cheng-Ying HUANG ,  Matthew V. METZ

IPC: H01L27/092 ,  H01L21/822 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS transistors having a group III-V material source/drain region.

公开(公告)号：US20200066855A1

公开(公告)日：2020-02-27

申请号：US16074373

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Glenn A. GLASS ,  Harold W. KENNEL ,  Anand S. MURTHY ,  Willy RACHMADY ,  Gilbert DEWEY ,  Sean T. MA ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/201

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

公开(公告)号：US20200066515A1

公开(公告)日：2020-02-27

申请号：US16303125

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Willy RACHMADY ,  Marc C. FRENCH ,  Seung Hoon SUNG ,  Jack T. KAVALIEROS ,  Matthew V. METZ ,  Ashish AGRAWAL

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.

公开(公告)号：US20190341481A1

公开(公告)日：2019-11-07

申请号：US16309049

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Willy RACHMADY ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Sean T. MA ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: An apparatus is described. The apparatus includes a FINFET transistor. The FINFET transistor comprises a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects along sidewalls of the subfin structure so that the defects are substantially prevented from reaching said FINFET transistor's channel.

公开(公告)号：US20190267289A1

公开(公告)日：2019-08-29

申请号：US16320425

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Sean T. MA ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Anand S. MURTHY ,  Harold W. KENNEL ,  Nicholas G. MINUTILLO ,  Jack T. KAVALIEROS ,  Willy RACHMADY

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.

公开(公告)号：US20190172941A1

公开(公告)日：2019-06-06

申请号：US16304620

申请日：2016-07-02

Applicant: INTEL CORPORATION

Inventor： Willy RACHMADY ,  Sanaz K. GARDNER ,  Chandra S. MOHAPATRA ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/775

Abstract: Embodiments are generally directed to a semiconductor device with released source and drain. An embodiment of a method includes etching a buffer layer of a semiconductor device to form a gate trench under a gate channel portion of a channel layer of the device; filling the gate trench with an oxide material to form an oxide isolation layer; etching one or more source/drain contact trenches in an interlayer dielectric (ILD) layer for source and drain regions of the device; etching the oxide isolation layer within the one or more source/drain contact trenches to form one or more cavities under a source/drain channel in the source and drain regions, wherein the etching of each contact trench is to expose all sides of the source/drain channel; and depositing contact metal in the one or more contact trenches, including depositing the contact metal in the cavities under the source/drain channel.