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    Memory devices based on capacitors with built-in electric field
    61.
    发明授权
    Memory devices based on capacitors with built-in electric field 有权

    公开(公告)号：US11171145B2

    公开(公告)日：2021-11-09

    申请号：US16016375

    申请日：2018-06-22

    Applicant: Intel Corporation

    Inventor： Sou-Chi Chang ,  Uygar Avci ,  Daniel H. Morris ,  Seiyon Kim ,  Ashish V. Penumatcha ,  Ian A. Young

    IPC: H01L27/115 ,  H01L27/11507 ,  H01L49/02 ,  G11C11/22

    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.

    IMPROPER FERROELECTRIC ACTIVE AND PASSIVE DEVICES
    64.
    发明申请
    IMPROPER FERROELECTRIC ACTIVE AND PASSIVE DEVICES 审中-公开

    公开(公告)号：US20200091308A1

    公开(公告)日：2020-03-19

    申请号：US16130903

    申请日：2018-09-13

    Applicant: Intel Corporation

    Inventor： Sasikanth Manipatruni ,  Uygar Avci ,  Sou-Chi Chang ,  Ian Young

    IPC: H01L29/51 ,  H01L29/78 ,  H01L27/11502 ,  H01L27/11585 ,  G11C11/22

    Abstract: A capacitor is provided which comprises: a first structure comprising metal; a second structure comprising metal; and a third structure between the first and second structures, wherein the third structure comprises an improper ferroelectric material. In some embodiments, a field effect transistor (FET) is provided which comprises: a substrate; a source and drain adjacent to the substrate; and a gate stack between the source and drain, wherein the gate stack includes: a dielectric; a first structure comprising improper ferroelectric material, wherein the first structure is adjacent to the dielectric; and a second structure comprising metal, wherein the second structure is adjacent to the first structure.

    TRANSFER OF A 2D MATERIAL TO A TARGET SUBSTRATE
    67.
    发明申请
    TRANSFER OF A 2D MATERIAL TO A TARGET SUBSTRATE 有权

    公开(公告)号：US20250113520A1

    公开(公告)日：2025-04-03

    申请号：US18375051

    申请日：2023-09-29

    Applicant: Intel Corporation

    Inventor： Andrey Vyatskikh ,  Paul Fischer ,  Paul Nordeen ,  Kevin O'Brien ,  Chelsey Dorow ,  Carl H. Naylor ,  Uygar Avci

    IPC: H01L29/775 ,  H01L21/762

    Abstract: Techniques and mechanisms for a transition metal dichalcogenide (TMD) material to be grown on one structure, and then transferred to a different structure. In an embodiment, one or more monolayers of a TMD material are grown on a workpiece comprising a substrate, a growth layer, and a release layer. A material of the substrate is transparent to a wavelength of a laser light, wherein the release layer is opaque to said wavelength. The resulting material stack is then coupled to a target structure, after which a laser ablation is performed to remove some or all of the release layer from between the substrate and the growth layer. The ablation enables the substrate to be separated from the one or more monolayers. In an embodiment, a residue on a surface of the one or more TMD monolayers is an artefact of the layer transfer process.

    SELF-ALIGNED MEMORY CELL WITH REPLACEMENT METAL GATE VERTICAL ACCESS TRANSISTOR AND STACKED 3D CAPACITORS
    69.
    发明申请
    SELF-ALIGNED MEMORY CELL WITH REPLACEMENT METAL GATE VERTICAL ACCESS TRANSISTOR AND STACKED 3D CAPACITORS 有权

    公开(公告)号：US20250008740A1

    公开(公告)日：2025-01-02

    申请号：US18216490

    申请日：2023-06-29

    Applicant: Intel Corporation

    Inventor： Wriddhi Chakraborty ,  Sourav Dutta ,  Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  Gilbert Dewey ,  Uygar Avci

    IPC: H10B53/20 ,  H10B53/30

    Abstract: An integrated circuit device includes a stack of capacitors with a vertical first electrode coupled to a stack of individual second electrodes by an insulating storage material between first and second electrodes, and an access transistor coaxially aligned with, and coupled to, the vertical first electrode. The storage material may be a ferroelectric material. A gate dielectric of the access transistor may be around, and coaxial with, a channel region. The channel region may be vertically oriented and coaxial with the first electrode. A second access transistor may be similarly aligned with the first electrode and the stack of capacitors with the capacitor stack between the transistors. A channel of the second transistor may be around, and coaxial with, a gate dielectric. The transistors and capacitor stack may be in arrays of transistors and capacitor stacks. A self-aligned process may be used to form the capacitor and transistor arrays.

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