公开(公告)号：US20230090106A1

公开(公告)日：2023-03-23

申请号：US17481253

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Paul B. FISCHER ,  Walid M. HAFEZ ,  Nicole K. THOMAS ,  Nityan NAIR ,  Pratik KOIRALA ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Thomas HOFF ,  Thoe MICHAELOS

IPC: H01L29/04 ,  H01L27/092 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/12 ,  H01L21/84

Abstract: Gallium nitride (GaN) layer transfer for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A first layer including gallium and nitrogen is over a first region of the substrate, the first layer having a gallium-polar orientation with a top crystal plane consisting of a gallium face. A second layer including gallium and nitrogen is over a second region of the substrate, the second layer having a nitrogen-polar orientation with a top crystal plane consisting of a nitrogen face.

公开(公告)号：US20220399445A1

公开(公告)日：2022-12-15

申请号：US17347034

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Conor P. PULS ,  Walid M. HAFEZ ,  Sairam SUBRAMANIAN ,  Justin S. SANDFORD ,  Saurabh MORARKA ,  Sean PURSEL ,  Mohammad HASAN

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234

Abstract: Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.

公开(公告)号：US20220359705A1

公开(公告)日：2022-11-10

申请号：US17871693

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/535

Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

公开(公告)号：US20210399002A1

公开(公告)日：2021-12-23

申请号：US16910020

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Walid M. HAFEZ ,  Rohan BAMBERY ,  Daniel B. O'Brien ,  Christopher Alan NOLPH ,  Rahul RAMASWAMY ,  Ting CHANG

IPC: H01L27/11568 ,  H01L49/02 ,  H01L29/78 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size.

公开(公告)号：US20210183857A1

公开(公告)日：2021-06-17

申请号：US16713703

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Rahul RAMASWAMY ,  Tanuj TRIVEDI ,  Jeong Dong KIM ,  Ting CHANG ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Nidhi NIDHI

IPC: H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/51 ,  H01L21/02

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such semiconductor devices. In an embodiment, the semiconductor device comprises a substrate, and a first transistor over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel above the substrate, a first gate dielectric surrounding the first semiconductor channel, and a first gate electrode over the first gate dielectric. In an embodiment, the semiconductor device further comprises a second transistor over the substrate. In an embodiment, the second transistor comprises a second semiconductor channel above the substrate, a second gate dielectric surrounding the second semiconductor channel, where the second gate dielectric is different than the first gate dielectric, and a second gate electrode over the second gate dielectric, where the first gate electrode and the second gate electrode comprise the same material.

公开(公告)号：US20200287015A1

公开(公告)日：2020-09-10

申请号：US16294307

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ

IPC: H01L29/49 ,  H01L27/088 ,  H01L23/535 ,  H01L21/8234

Abstract: Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

公开(公告)号：US20200273887A1

公开(公告)日：2020-08-27

申请号：US15931881

申请日：2020-05-14

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Jeng-Ya D. YEH ,  Curtis TSAI ,  Joodong PARK ,  Chia-Hong JAN ,  Gopinath BHIMARASETTI

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

公开(公告)号：US20190305112A1

公开(公告)日：2019-10-03

申请号：US15943556

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/088

Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US20190305111A1

公开(公告)日：2019-10-03

申请号：US15943552

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Christopher KENYON ,  Sridhar GOVINDARAJU ,  Chia-Hong JAN ,  Mark LIU ,  Szuya S. LIAO ,  Walid M. HAFEZ

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

公开(公告)号：US20190304840A1

公开(公告)日：2019-10-03

申请号：US16317265

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chen-Guan LEE ,  Everett S. CASSIDY-COMFORT ,  Joodong PARK ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Rahul RAMASWAMY ,  Neville L. DIAS ,  Hsu-Yu CHANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/3115 ,  H01L29/66

Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.