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    Memory Cell Having an Integrated Two-Terminal Current Limiting Resistor
    62.
    发明申请
    Memory Cell Having an Integrated Two-Terminal Current Limiting Resistor 有权
    具有集成两端限流电阻的存储单元

    公开(公告)号：US20130221315A1

    公开(公告)日：2013-08-29

    申请号：US13721310

    申请日：2012-12-20

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

    IPC: H01L45/00

    CPC classification number: H01L45/12 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

    Abstract translation: 提供了一种结合到具有改进的性能和寿命的电阻式开关存储单元中的电阻器结构。 电阻器结构可以是设计成减小流过存储器单元的最大电流的两端结构。 还提供了一种用于制造这种存储单元的方法。 该方法包括沉积电阻器结构并沉积存储单元的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联布置以限制存储单元的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器单元的开关规范的期望的开关电流水平是非常有用的。 存储单元可以形成为可用于各种电子设备的大容量非易失性存储器集成电路的一部分。

    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate
    63.
    发明申请
    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 失效
    在半导体基板上筛选多个样品的组合处理方法

    公开(公告)号：US20130138380A1

    公开(公告)日：2013-05-30

    申请号：US13731715

    申请日：2012-12-31

    Applicant: INTERMOLECULAR, INC.

    Inventor： Guarav Verma ,  Tony P. Chiang ,  Imran Hashim ,  Sandra G. Malhotra ,  Prashant B. Phatak ,  Kurt H. Weiner

    IPC: G01R31/28

    CPC classification number: G01R31/2831 ,  G01R31/2834 ,  H01L22/34

    Abstract: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

    Abstract translation: 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

    Molecular Self-Assembly in Substrate Processing
    64.
    发明申请
    Molecular Self-Assembly in Substrate Processing 有权
    基板加工中的分子自组装

    公开(公告)号：US20130099363A1

    公开(公告)日：2013-04-25

    申请号：US13717378

    申请日：2012-12-17

    Applicant: Intermolecular, Inc.

    Inventor： Tony P. Chiang ,  Majid Keshavarz ,  David E. Lazovsky

    IPC: H01L21/31 ,  H01L29/06

    CPC classification number: H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

    Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

    Abstract translation: 提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。 在一些实施方案中，存在方法，其中有机硅烷包括：炔基，芳基，氟代烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基。 在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。

    Nonvolatile Memory Elements with Metal-Deficient Resistive-Switching Metal Oxides
    65.
    发明申请
    Nonvolatile Memory Elements with Metal-Deficient Resistive-Switching Metal Oxides 有权
    具有金属缺陷电阻开关金属氧化物的非易失性存储元件

    公开(公告)号：US20130071982A1

    公开(公告)日：2013-03-21

    申请号：US13675695

    申请日：2012-11-13

    Applicant: Intermolecular, Inc.

    Inventor： Nitin Kumar ,  Tony P. Chiang ,  Chi-I Lang ,  Prashant B. Phatak ,  Jinhong Tong

    IPC: H01L45/00

    CPC classification number: G11C13/0007 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

    Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal.

    Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以通过将含金属的材料沉积在含硅材料上而形成。 含金属材料可以被氧化以形成电阻式开关金属氧化物。 当施加热量时，含硅材料中的硅与含金属材料中的金属反应。 这形成用于非易失性存储元件的金属硅化物下电极。 上部电极可以沉积在金属氧化物的顶部。 由于含硅层中的硅与含金属层中的一些金属反应，与由相同金属形成的化学计量的金属氧化物相比，形成的电阻 - 开关金属氧化物是金属缺陷的。

    MOLECULAR SELF-ASSEMBLY IN SUBSTRATE PROCESSING
    69.
    发明申请
    MOLECULAR SELF-ASSEMBLY IN SUBSTRATE PROCESSING 审中-公开
    分子自组装在基板加工中

    公开(公告)号：US20160042991A1

    公开(公告)日：2016-02-11

    申请号：US14885002

    申请日：2015-10-16

    Applicant: Intermolecular Inc.

    Inventor： Tony P. Chiang ,  Majid Keshavarz ,  David E. Lazovsky

    IPC: H01L21/768

    CPC classification number: H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

    Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

    Abstract translation: 提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。 在一些实施方案中，存在方法，其中有机硅烷包括：炔基，芳基，氟烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基。 在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。

    Nonvolatile memory device having an electrode interface coupling region
    70.
    发明授权
    Nonvolatile memory device having an electrode interface coupling region 有权
    具有电极接口耦合区域的非易失性存储器件

    公开(公告)号：US09184383B2

    公开(公告)日：2015-11-10

    申请号：US14156762

    申请日：2014-01-16

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

    Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

    Abstract translation: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成 器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

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