公开(公告)号：US20150236260A1

公开(公告)日：2015-08-20

申请号：US14702374

申请日：2015-05-01

Applicant: Intermolecular Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E. Lazovsky

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract translation: 本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极 第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。 第二电极设置在嵌入式电阻式存储单元内靠近第一电极。 第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。 第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层和设置在高k电介质层上方的金属层。

公开(公告)号：US09368400B2

公开(公告)日：2016-06-14

申请号：US14625488

申请日：2015-02-18

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  David E. Lazovsky ,  Sandra G. Malhotra

IPC: H01L21/44 ,  H01L21/768 ,  B82Y30/00 ,  H01L21/02 ,  H01L21/288 ,  H01L21/31

CPC classification number: H01L21/7685 ,  B82Y30/00 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/288 ,  H01L21/31 ,  H01L21/76834

Abstract: A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, can be used to form the masking layer. The capping layer can be formed of an conductive material, a semiconductor material, or an insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

公开(公告)号：US20160042991A1

公开(公告)日：2016-02-11

申请号：US14885002

申请日：2015-10-16

Applicant: Intermolecular Inc.

Inventor： Tony P. Chiang ,  Majid Keshavarz ,  David E. Lazovsky

IPC: H01L21/768

CPC classification number: H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract translation: 提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。 在一些实施方案中，存在方法，其中有机硅烷包括：炔基，芳基，氟烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基。 在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。

公开(公告)号：US20150056723A1

公开(公告)日：2015-02-26

申请号：US14507209

申请日：2014-10-06

Applicant: Intermolecular, Inc.

Inventor： David E. Lazovsky ,  Tony P. Chiang ,  Sandra G. Malhotra

IPC: H01L21/66

CPC classification number: H01L22/26 ,  H01L21/32051 ,  H01L21/67028 ,  H01L21/6708 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/76834 ,  H01L21/76841 ,  H01L21/76849 ,  H01L21/76871

Abstract: Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate.

Abstract translation: 描述了用于处理具有两个或更多个区域的基板的基板处理系统和方法。 该处理包括分子自组装和组合处理中的一种或多种。 材料，工艺，加工条件，材料应用顺序和工艺顺序中的至少一个不同于衬底相对于衬底的至少一个其它区域的至少一个区域中的处理。 描述了包括许多处理模块的处理系统。 模块包括配置用于衬底的分子自组装和组合处理中的一个或多个的位点隔离反应器（SIR）。

公开(公告)号：US20140070213A1

公开(公告)日：2014-03-13

申请号：US14077137

申请日：2013-11-11

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  Tony P. Chiang ,  Alexander Gorer ,  David E. Lazovsky

IPC: H01L21/66

CPC classification number: H01L21/67011 ,  C23C14/54 ,  C23C16/4412 ,  C23C16/45544 ,  C23C16/4557 ,  C23C16/45578 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32513 ,  H01J37/32724 ,  H01J2237/166 ,  H01J2237/20228 ,  H01J2237/20235 ,  H01L21/6715 ,  H01L21/76849 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/907 ,  Y10S438/913 ,  Y10T137/8593 ,  H01L2924/00

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract translation: 本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。 通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

公开(公告)号：US20150021774A1

公开(公告)日：2015-01-22

申请号：US14507328

申请日：2014-10-06

Applicant: Intermolecular, Inc.

Inventor： Tony P. Chiang ,  Majid Keshavarz ,  David E. Lazovsky

IPC: H01L23/532

CPC classification number: H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract translation: 提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。 在一些实施方案中，存在有机硅烷包括：炔基，芳基，氟烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基的方法。 在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。

公开(公告)号：US08815753B2

公开(公告)日：2014-08-26

申请号：US13717378

申请日：2012-12-17

Applicant: Intermolecular, Inc.

Inventor： Tony P. Chiang ,  Majid Keshavarz ,  David E. Lazovsky

IPC: H01L21/31

CPC classification number: H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract translation: 提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。 在一些实施方案中，存在方法，其中有机硅烷包括：炔基，芳基，氟代烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基。 在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。

公开(公告)号：US20140230955A1

公开(公告)日：2014-08-21

申请号：US14261191

申请日：2014-04-24

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  Tony P. Chiang ,  Alexander Gorer ,  David E. Lazovsky ,  Thomas H. McWaid

IPC: B01J19/00

CPC classification number: B01J19/0046 ,  B01J2219/00286 ,  B01J2219/00317 ,  B01J2219/00328 ,  B01J2219/00333 ,  B01J2219/00351 ,  B01J2219/00364 ,  B01J2219/00369 ,  B01J2219/00495 ,  B01J2219/00527 ,  B01J2219/00603 ,  B01J2219/00659 ,  B01J2219/00691 ,  H01L21/76849

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract translation: 本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。 通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

公开(公告)号：US08610121B2

公开(公告)日：2013-12-17

申请号：US13661501

申请日：2012-10-26

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  Tony P. Chiang ,  Alexander Gorer ,  David E. Lazovsky

IPC: H01L21/00

CPC classification number: H01L21/67011 ,  C23C14/54 ,  C23C16/4412 ,  C23C16/45544 ,  C23C16/4557 ,  C23C16/45578 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32513 ,  H01J37/32724 ,  H01J2237/166 ,  H01J2237/20228 ,  H01J2237/20235 ,  H01L21/6715 ,  H01L21/76849 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/907 ,  Y10S438/913 ,  Y10T137/8593 ,  H01L2924/00

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

公开(公告)号：US20130099363A1

公开(公告)日：2013-04-25

申请号：US13717378

申请日：2012-12-17

Applicant: Intermolecular, Inc.

Inventor： Tony P. Chiang ,  Majid Keshavarz ,  David E. Lazovsky

IPC: H01L21/31 ,  H01L29/06

CPC classification number: H01L23/5329 ,  B82Y30/00 ,  H01L21/31 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76879 ,  H01L28/65 ,  H01L29/06 ,  H01L2924/0002 ,  Y10T428/249953 ,  H01L2924/00

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract translation: 提供了密封多孔电介质的方法，包括：接收衬底，所述衬底包括多孔电介质; 将基板暴露于有机硅烷中，其中有机硅烷包括用于促进与多孔电介质附着的可水解基团，并且其中有机硅烷不包括烷基; 并且由于暴露而形成层以密封多孔电介质。 在一些实施方案中，存在方法，其中有机硅烷包括：炔基，芳基，氟代烷基，杂芳基，醇基，硫醇基，胺基，硫代氨基甲酸酯基，酯基，醚基，硫醚基和腈基。 在一些实施例中，方法还包括：在暴露之前从多孔电介质和衬底的导电区域去除污染物; 并且在成形之后从导电区域去除污染物。