公开(公告)号：US09054020B2

公开(公告)日：2015-06-09

申请号：US13686969

申请日：2012-11-28

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/76 ,  H01L29/16 ,  H01L21/308

CPC classification number: H01L29/16 ,  H01L21/3086 ,  H01L21/845 ,  H01L27/1211

Abstract: Methods and structures having increased fin density are disclosed. Structures with two sets of fins are provided. A lower set of fins is interleaved with an upper set of fins in a staggered manner, such that the lower set of fins and upper set of fins are horizontally and vertically non-overlapping.

Abstract translation: 公开了具有增加的翅片密度的方法和结构。 提供具有两组翅片的结构。 下一组翅片以交错的方式与上部翅片交错，使得下部翅片组和上部翅片组水平和垂直不重叠。

公开(公告)号：US20150144886A1

公开(公告)日：2015-05-28

申请号：US14605009

申请日：2015-01-26

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

公开(公告)号：US20150054077A1

公开(公告)日：2015-02-26

申请号：US13972032

申请日：2013-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material.

公开(公告)号：US20150031201A1

公开(公告)日：2015-01-29

申请号：US14512718

申请日：2014-10-13

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Chiahsun Tseng ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L21/308 ,  H01L21/768

CPC classification number: H01L21/3083 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure.

Abstract translation: 一种包括在衬底上形成四层硬掩模的方法，所述四层硬掩模包括在第一硬掩模层上方的第二硬掩模层; 在包括所述基底和所述四层硬掩模的结构的图案区域内去除所述四层硬掩模的所述第二硬掩模层的一部分; 在所述四层硬掩模之上形成一组侧壁间隔物以限定器件图案; 以及将所述器件图案的一部分转移到所述衬底中并且在所述结构的图案区域内。

公开(公告)号：US20140377917A1

公开(公告)日：2014-12-25

申请号：US13954453

申请日：2013-07-30

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Junli Wang ,  Yunpeng Yin

IPC: H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device having a doped well area includes a doped substrate layer formed on a substrate portion of the semiconductor device. The doped substrate layer extends along a first direction to define a length and a second direction perpendicular to the first direction to define a width. A plurality of fins is formed on the doped substrate layer and an oxide substrate layer is formed between each fin. At least one gate is formed on the oxide substrate layer and extends across at least one fin among the plurality of fins.

公开(公告)号：US20140315379A1

公开(公告)日：2014-10-23

申请号：US14027315

申请日：2013-09-16

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/28

CPC classification number: H01L21/28132 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.

公开(公告)号：US08859384B1

公开(公告)日：2014-10-14

申请号：US13957022

申请日：2013-08-01

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung H. Chen ,  Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/20 ,  H01L49/02

CPC classification number: H01L28/10

Abstract: Methods for forming inductors. The methods include forming sidewalls around a mandrel over a conductor layer; removing material from the conductor layer around a region defined by the sidewalls; removing the mandrel; partially etching the conductor layer in a region between the sidewalls; etching the partially etched conductor layer to form separate metal segments; depositing a dielectric material in and around the metal segments; and forming conductive lines between exposed contacts of adjacent metal segments.

Abstract translation: 电感器形成方法。 所述方法包括在导体层上形成围绕心轴的侧壁; 在由侧壁限定的区域周围从导体层去除材料; 去除心轴; 在侧壁之间的区域中部分地蚀刻导体层; 蚀刻部分蚀刻的导体层以形成分离的金属段; 在金属片段内和周围沉积电介质材料; 以及在相邻金属段的暴露的触点之间形成导电线。

公开(公告)号：US20140264596A1

公开(公告)日：2014-09-18

申请号：US13831172

申请日：2013-03-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545

Abstract: A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates.

公开(公告)号：US20140256139A1

公开(公告)日：2014-09-11

申请号：US14284792

申请日：2014-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin ,  Lei L. Zhuang

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L21/30604 ,  H01L21/0334 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/3088

Abstract: A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery.

Abstract translation: 通过从第一硬掩模层和第二硬掩模层的从底部到顶部的各向异性地蚀刻叠层，在半导体材料层上形成第一硬掩模部分和第二硬掩模部分的堆叠。 通过各向同性蚀刻，第一硬掩模部分被横向凹进。 电介质材料层被共形沉积并平坦化。 使用对第一硬掩模部分选择性的各向异性蚀刻蚀刻电介质材料层，以形成侧向围绕第一硬掩模部分的电介质材料部分。 在去除第二和第一硬掩模部分之后，使用介电材料部分作为蚀刻掩模蚀刻半导体材料层。 可选地，第一和第二硬掩模部分下面的半导体材料层的一部分可以在周边被切削。

公开(公告)号：US09985030B2

公开(公告)日：2018-05-29

申请号：US14581135

申请日：2014-12-23

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/8238 ,  H01L27/092 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L27/0924 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough.