公开(公告)号：US10553679B2

公开(公告)日：2020-02-04

申请号：US15834380

申请日：2017-12-07

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Takashi Ando ,  Choonghyun Lee ,  Alexander Reznicek ,  Pouya Hashemi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L29/417 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/223 ,  H01L21/321

Abstract: A semiconductor structure containing a gate-all-around nanosheet field effect transistor having a self-limited inner spacer composed of a rare earth doped germanium dioxide that provides source/drain isolation between rare earth metal silicide ohmic contacts is provided.

公开(公告)号：US10546925B2

公开(公告)日：2020-01-28

申请号：US15801967

申请日：2017-11-02

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Takashi Ando ,  Jingyun Zhang ,  Choonghyun Lee ,  Pouya Hashemi

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/16 ,  H01L29/423 ,  H01L29/08 ,  H01L29/49 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/285 ,  H01L27/12 ,  H01L29/786 ,  H01L21/84

Abstract: A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.

公开(公告)号：US20200027991A1

公开(公告)日：2020-01-23

申请号：US16037993

申请日：2018-07-17

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Juntao Li

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/51

Abstract: Techniques for reducing work function metal variability along the channel of VFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source/drains at a base of the fins and bottom spacers on the bottom source/drains; forming gate stacks over the fins including a gate conductor having a combination of work function metals including an outer layer and at least one inner layer of the work function metals; isotropically etching the work function metals which recesses the gate stacks with an outwardly downward sloping profile; isotropically etching the at least one inner layer while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks; forming top spacers above the gate stacks; and forming top source and drains at tops of the fins. A VTFET device is also provided.

公开(公告)号：US20200013900A1

公开(公告)日：2020-01-09

申请号：US16026521

申请日：2018-07-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Adra Carr ,  Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi

IPC: H01L29/786 ,  H01L21/768 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/45

Abstract: A method of forming a source/drain contact is provided. The method includes forming a sacrificial layer on a source/drain, and depositing an oxidation layer on the sacrificial layer. The method further includes heat treating the oxidation layer and the sacrificial layer to form a modified sacrificial layer. The method further includes forming a protective liner on the modified sacrificial layer, and depositing an interlayer dielectric layer on the protective liner. The method further includes forming a trench in the interlayer dielectric layer that exposes a portion of the protective liner.

公开(公告)号：US20200013879A1

公开(公告)日：2020-01-09

申请号：US16029133

申请日：2018-07-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao Li ,  Kangguo Cheng ,  Choonghyun Lee ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/8234

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin on a substrate, and depositing a sidewall liner on exposed surfaces of the vertical fin. The method further includes removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin. The method further includes laterally etching the support pillar to form a thinned support pillar, and forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness.

公开(公告)号：US20200006147A1

公开(公告)日：2020-01-02

申请号：US16564705

申请日：2019-09-09

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee

IPC: H01L21/8258 ,  H01L27/092 ,  H01L21/225

Abstract: Embodiments of the invention are directed to fin-based field effect transistor (FET) devices formed on a substrate. In a non-limiting example, the devices a first fin formed in a p-type FET (PFET) region of the substrate, wherein the first fin includes a top region, a central region, and a bottom region. The central region of the first fin includes an epitaxial first material in-situ doped with a first type of semiconductor material at a first concentration level. The top region of the first fin includes the epitaxial first material in-situ doped with the first type of semiconductor material at the first concentration level, along with an anneal-induced second concentration level of the first type of semiconductor material. A final concentration level of the first type of semiconductor material in the top region includes the first concentration level and the second concentration level.

公开(公告)号：US20200006146A1

公开(公告)日：2020-01-02

申请号：US16021377

申请日：2018-06-28

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Choonghyun Lee

IPC: H01L21/8258 ,  H01L27/092 ,  H01L21/225

Abstract: Embodiments of the invention are directed to a method of fabricating semiconductor devices. A non-limiting example of the method includes forming a first fin in a p-type field effect transistor (PFET) region of a substrate, wherein the first fin includes a first material that includes a first type of semiconductor material at a first concentration level. A second fin is formed in an n-type FET (NFET) region of the substrate, wherein the second fin includes a second semiconductor material that includes a III-V compound. Condensation operations are performed, wherein the condensation operations are configured to increase the first concentration level in at least a portion of the first fin to a targeted final concentration level.

公开(公告)号：US10522649B2

公开(公告)日：2019-12-31

申请号：US15965264

申请日：2018-04-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.

公开(公告)号：US20190393306A1

公开(公告)日：2019-12-26

申请号：US16561983

申请日：2019-09-05

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Takashi Ando ,  Choonghyun Lee ,  Alexander Reznicek ,  Pouya Hashemi

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/321 ,  H01L21/223 ,  H01L21/324 ,  H01L21/02 ,  H01L21/306 ,  H01L29/417 ,  H01L29/45 ,  H01L29/423

Abstract: A semiconductor structure containing a gate-all-around nanosheet field effect transistor having a self-limited inner spacer composed of a rare earth doped germanium dioxide that provides source/drain isolation between rare earth metal silicide ohmic contacts is provided.

公开(公告)号：US20190386102A1

公开(公告)日：2019-12-19

申请号：US16455096

申请日：2019-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao Li ,  Kangguo Cheng ,  Choonghyun Lee ,  Peng Xu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08

Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin layer on a bottom source/drain layer, and forming one or more fin templates on the vertical fin layer. The method further includes forming a vertical fin below each of the one or more fin templates. The method further includes reducing the width of each of the vertical fins to form one or more thinned vertical fins, wherein at least a portion of the fin template overhangs the sides of the underlying thinned vertical fin. The method further includes depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness that tapers in a direction towards the thinned vertical fins.