公开(公告)号：US11823998B2

公开(公告)日：2023-11-21

申请号：US17475702

申请日：2021-09-15

Applicant: International Business Machines Corporation

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Nicholas Anthony Lanzillo ,  Kisik Choi ,  Robert Robison

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76871 ,  H01L21/76877

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.

公开(公告)号：US11757012B2

公开(公告)日：2023-09-12

申请号：US16687736

申请日：2019-11-19

Applicant: International Business Machines Corporation

Inventor： Andrew Greene ,  Dechao Guo ,  Tenko Yamashita ,  Veeraraghavan S. Basker ,  Robert Robison ,  Ardasheir Rahman

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/456 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

公开(公告)号：US11682617B2

公开(公告)日：2023-06-20

申请号：US17129971

申请日：2020-12-22

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Somnath Ghosh ,  Lawrence A. Clevenger ,  Robert Robison

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295 ,  H01L21/7682 ,  H01L23/5222

Abstract: An interlayer interconnect for an integrated circuit includes a first line in a first wiring layer, a first via portion integral to and extending from the first line, and a second line in a second wiring layer that is adjacent to the first wiring layer. The interlayer interconnect also includes a third line in the second wiring layer that is a first distance from the second line, wherein the first distance is a pitch of the second wiring layer, and a second via portion integral to and extending from the second line and in electrical contact with the first via portion at an interface to form a via. The via extends a second distance that is at least one-and-a-quarter times the pitch.

公开(公告)号：US20230178621A1

公开(公告)日：2023-06-08

申请号：US17544328

申请日：2021-12-07

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Reinaldo Vega ,  Yao Yao ,  Andrew M. Greene ,  Veeraraghavan S. Basker ,  Pietro Montanini ,  Jingyun Zhang ,  Robert Robison

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/823412 ,  H01L21/823418

Abstract: A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further includes a source/drain region contact in physical contact with the V shaped internal recess, with the front surface, and with the rear surface. The device may be fabricated by forming the source/drain region, recessing the source/drain region, and by forming a sacrificial source/drain region upon and around the recessed source/drain region. The sacrificial source/drain region may be removed and the source/drain region contact may be formed in place thereof.

公开(公告)号：US20230139399A1

公开(公告)日：2023-05-04

申请号：US17516505

申请日：2021-11-01

Applicant: International Business Machines Corporation

Inventor： HUIMEI ZHOU ,  Andrew M. Greene ,  Michael P. Belyansky ,  Oleg Gluschenkov ,  Robert Robison ,  JUNTAO LI ,  Richard A. Conti ,  FEE LI LIE

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L21/762

Abstract: A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

公开(公告)号：US20230067119A1

公开(公告)日：2023-03-02

申请号：US17446784

申请日：2021-09-02

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Robert Robison ,  Hemanth Jagannathan ,  Jay William Strane

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: A self-aligned C-shaped vertical field effect transistor includes a semiconductor substrate having an uppermost surface and a fin structure on the uppermost surface of the semiconductor substrate. The fin structure has two adjacent vertical segments with rounded ends that extend perpendicularly from the uppermost surface of the semiconductor substrate and a horizontal segment that extends between and connects the two adjacent vertical segments. An opening is located between the two adjacent vertical segments on a side of the fin structure opposite to the horizontal segment.

公开(公告)号：US11527434B2

公开(公告)日：2022-12-13

申请号：US16796079

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Mathew Philip ,  Daniel James Dechene ,  Somnath Ghosh ,  Robert Robison

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3213

Abstract: A method for fabricating a semiconductor device includes forming a first line pattern within sacrificial mandrel material disposed on at least one hard mask layer disposed on a substrate. The first line pattern has a pitch defined by a target line width and a minimum width of space between lines. The method further includes forming, within the first line pattern, a first spacer having a width corresponding to the minimum width of space between lines to minimize pinch points and a first gap having the target line width, and forming a first plug within the first gap corresponding to a first location above the at least one hard mask layer to block pattern transfer into the at least one hard mask layer.

公开(公告)号：US11430735B2

公开(公告)日：2022-08-30

申请号：US16791400

申请日：2020-02-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Alan Anderson ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Lawrence A. Clevenger ,  Kisik Choi ,  Robert Robison

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: A multi-layer device comprising a barrier or adhesion layer located on a portion of a first top surface of a first layer, a conductive metal layer located on barrier or adhesion layer; and a dielectric layer located on top of the first layer, wherein the dielectric layer is in direct contact with the sidewall of the conductive metal layer.

公开(公告)号：US20220157652A1

公开(公告)日：2022-05-19

申请号：US17592078

申请日：2022-02-03

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L45/00 ,  H01L27/146 ,  H01L21/02

Abstract: A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.

公开(公告)号：US20220108922A1

公开(公告)日：2022-04-07

申请号：US17551531

申请日：2021-12-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Koichi Motoyama ,  Somnath Ghosh ,  Christopher J. Penny ,  Robert Robison ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.