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110 条记录 (耗时 0.024 秒)

    MULTICHIP PACKAGE LINK ERROR DETECTION
    66.
    发明申请
    MULTICHIP PACKAGE LINK ERROR DETECTION 有权

    公开(公告)号：US20220350698A1

    公开(公告)日：2022-11-03

    申请号：US17721290

    申请日：2022-04-14

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

    IPC分类号： G06F11/10 ,  H04L1/00 ,  H04L1/20 ,  H04L9/40 ,  G06F13/16

    摘要： First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

    Extending multichip package link off package
    67.
    发明授权
    Extending multichip package link off package 有权

    公开(公告)号：US11386033B2

    公开(公告)日：2022-07-12

    申请号：US17121534

    申请日：2020-12-14

    申请人： Intel Corporation

    发明人： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

    IPC分类号： G06F13/40 ,  H01L25/065 ,  G06F13/42 ,  H01L23/538

    摘要： An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

    MULTICHIP PACKAGE LINK ERROR DETECTION
    68.
    发明申请
    MULTICHIP PACKAGE LINK ERROR DETECTION 审中-公开

    公开(公告)号：US20200319957A1

    公开(公告)日：2020-10-08

    申请号：US16779391

    申请日：2020-01-31

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

    IPC分类号： G06F11/10 ,  H04L29/06 ,  H04L1/00 ,  H04L1/20 ,  G06F13/16

    摘要： First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

    High performance interconnect physical layer
    69.
    发明授权
    High performance interconnect physical layer 有权

    公开(公告)号：US10795841B2

    公开(公告)日：2020-10-06

    申请号：US16284742

    申请日：2019-02-25

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  Darren Jue ,  Sitaraman Iyer

    IPC分类号： G06F13/40 ,  G06N20/00 ,  G06F13/42

    摘要： A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    70.
    发明申请
    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 审中-公开

    公开(公告)号：US20200293480A1

    公开(公告)日：2020-09-17

    申请号：US16802209

    申请日：2020-02-26

    申请人： INTEL CORPORATION

    发明人： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

    摘要： Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.