公开(公告)号：US20110188968A1

公开(公告)日：2011-08-04

申请号：US12744153

申请日：2008-05-23

申请人： Zhiqiang Wu ,  Shaofan Zeng ,  Xiangyong Zhong

发明人： Zhiqiang Wu ,  Shaofan Zeng ,  Xiangyong Zhong

IPC分类号： F16B37/08

CPC分类号： B60S9/08

摘要： A semi-trailer leg loading nut includes a screwed hole provided on a nut column and connecting two ends of the nut. Said nut is a two-layered structure formed of a top layer and an under layer or a three-layered structure formed of a top layer, an intermediate layer and an under layer. The outer outline of at least two layers of the nut is a square with the same cutting angle. The side length of the two layers of squares is equal. The outer outline projection of the two layers of squares overlap with each other along the column axis direction. The outer outline projection of the other layer is within the overlapped projection of the two layers along the column axis direction. A funneled oil cup or an oil groove is provided on the top layer of the nut and communicates with the screwed hole. A bottom of the under layer of the nut is plane and is pressed on a loading plate in a quadrate pipe to transfer load.

摘要翻译： 半挂车小腿装载螺母包括设在螺母柱上并连接螺母两端的螺纹孔。 所述螺母是由顶层和下层或由顶层，中间层和下层形成的三层结构形成的两层结构。 螺母的至少两层的外轮廓是具有相同切割角度的正方形。 两层正方形的边长相等。 两层正方形的外轮廓投影沿柱轴方向相互重叠。 另一层的外轮廓投影在两列沿着列轴方向的重叠投影内。 漏斗油杯或油槽设置在螺母的顶层上，并与螺纹孔连通。 螺母底层的底部是平面的，并被压在方管中的装载板上以传递负载。

公开(公告)号：US20100022062A1

公开(公告)日：2010-01-28

申请号：US12573450

申请日：2009-10-05

申请人： Kaiping Liu ,  Zhiqiang Wu ,  Majid Movahed Mansoorz

发明人： Kaiping Liu ,  Zhiqiang Wu ,  Majid Movahed Mansoorz

IPC分类号： H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/823828 ,  H01L29/4983

摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

摘要翻译： 本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。 在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。 晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

公开(公告)号：US20070004158A1

公开(公告)日：2007-01-04

申请号：US11469687

申请日：2006-09-01

申请人： Kaiping Liu ,  Zhiqiang Wu ,  Majid Mansoorz

发明人： Kaiping Liu ,  Zhiqiang Wu ,  Majid Mansoorz

IPC分类号： H01L29/80 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/823828 ,  H01L29/4983

摘要： The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

摘要翻译： 本发明提供一种具有位于其中的锗注入区域170的晶体管100及其制造方法，以及包括上述晶体管的集成电路。 在一个实施例中，晶体管100包括位于半导体衬底110上方的多晶硅栅电极140，其中多晶硅栅电极140的侧壁上具有锗注入区170。 晶体管100还包括靠近多晶硅栅电极140位于半导体衬底110内的源/漏区160。

公开(公告)号：US20050212041A1

公开(公告)日：2005-09-29

申请号：US11127941

申请日：2005-05-11

申请人： Zhiqiang Wu ,  Jihong Chen ,  Kaiping Liu

发明人： Zhiqiang Wu ,  Jihong Chen ,  Kaiping Liu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/2652 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7833

摘要： A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.

摘要翻译： 提出了一种形成相关晶体管的方法，从而减轻了短沟道效应和结电容，从而促进了切换速度的提高。 通过在衬底内形成的源区和漏区相对深地注入掺杂剂，在衬底内形成补偿区。 补偿区域比源极和漏极区域稍微间隔开。 该间隔影响电位轮廓并降低晶体管内的结电容。 通过形成和选择性地调节与晶体管的栅极结构相邻的侧壁间隔来实现源极和漏极区域与补偿区域之间的不同距离。 这些间隔物用作植入衬底中的掺杂剂以形成源区和漏区以及补偿区的引导。

公开(公告)号：US06933203B2

公开(公告)日：2005-08-23

申请号：US10299525

申请日：2002-11-19

申请人： Zhiqiang Wu ,  Shaoping Tang ,  Jau-Yuann Yang

发明人： Zhiqiang Wu ,  Shaoping Tang ,  Jau-Yuann Yang

IPC分类号： H01L21/761 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/00

CPC分类号： H01L21/76237 ,  H01L21/761 ,  H01L21/823481

摘要： Methods are provided for forming wells in a semiconductor wafer, in which p-wells and n-wells are formed in a substrate, and first p-type dopants are implanted into n-well regions while an n-well mask remains over the wafer to selectively decrease a substrate resistivity in the n-well regions beneath the n-wells. A subsequent blanket implantation provides second p-type dopants into isolation regions of the substrate beneath isolation structures, where the first and second p-type dopants improve well to well isolation without addition of extra masks to the fabrication process.

摘要翻译： 提供了用于在半导体晶片中形成阱的方法，其中在衬底中形成p阱和n阱，并且将第一p型掺杂剂注入到n阱区域中，同时n阱掩模保留在晶片上， 选择性地降低n阱下面的n阱区中的衬底电阻率。 随后的覆盖植入在隔离结构下方的衬底的隔离区域中提供第二p型掺杂剂，其中第一和第二p型掺杂剂改善了良好的良好隔离，而没有向制造工艺添加额外的掩模。

公开(公告)号：US06855984B1

公开(公告)日：2005-02-15

申请号：US10697510

申请日：2003-10-30

申请人： Zhiqiang Wu ,  Shaoping Tang ,  Song Zhao

发明人： Zhiqiang Wu ,  Shaoping Tang ,  Song Zhao

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/7833

摘要： The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profile or transition from a portion of the active regions to the channel. However, the blanket implant is performed at a relatively low energy so as to not significantly alter one or more other portions of the active regions to other portions of the device.

摘要翻译： 本发明在NMOS器件中形成有源区之后采用n型注入的无掩模，覆盖式注入。 结果，注入的n型掺杂剂抵消了强p型HALO或凹坑区域的部分，从而产生了更平滑的掺杂物分布或从有源区域的一部分到沟道的转变。 然而，橡皮布注入在相对较低的能量下进行，以便不会将活性区的一个或多个其它部分显着地改变到该装置的其它部分。

公开(公告)号：US06831337B2

公开(公告)日：2004-12-14

申请号：US10622052

申请日：2003-07-17

申请人： Zhiqiang Wu ,  David B. Scott

发明人： Zhiqiang Wu ,  David B. Scott

IPC分类号： H01L2972

CPC分类号： H01L29/66659 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/7835

摘要： A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

摘要翻译： 一种在半导体有源区（78）中形成晶体管（70）的方法。 该方法形成与半导体有源区域固定关系的栅极结构（G2），从而限定与第一栅极结构侧壁相邻的第一源极/漏极区域（R1）和邻近第二侧壁栅极的第二源极/漏极区域（R2） 结构体。 该方法还形成在第一源极/漏极区域中形成并在栅极结构下方延伸的轻掺杂扩散区域（801），其中轻掺杂扩散区域包括与栅极结构平行的方向上的变化的电阻。

公开(公告)号：US06794235B1

公开(公告)日：2004-09-21

申请号：US10455088

申请日：2003-06-05

申请人： Kaiping Liu ,  Zhiqiang Wu

发明人： Kaiping Liu ,  Zhiqiang Wu

IPC分类号： H01L218238

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/66537 ,  H01L29/78

摘要： The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device 200 includes a gate 244 located over a substrate 210, the substrate 210 having a source and a drain 230 located therein. In the same embodiment, located adjacent each of the source and drain 230 are localized halo implants 250, each of the localized halo implants 250 having a vertical implant region 260 and an angled implant region 265. Further, at an intersection of the vertical implant region 260 and the angled implant region 265 is an area of peak concentration.

摘要翻译： 本发明提供一种半导体器件200，其具有位于其中的局部晕轮植入物250，因此制造方法以及包括该半导体器件的集成电路。 在一个实施例中，半导体器件200包括位于衬底210上的栅极244，衬底210具有位于其中的源极和漏极230。 在相同的实施例中，位于源极和漏极230的每一个附近的是局部晕轮注入250，每个局部晕轮植入物250具有垂直注入区域260和倾斜注入区域265.此外，在垂直注入区域 260和角度注入区域265是峰值浓度的区域。

公开(公告)号：US06788552B1

公开(公告)日：2004-09-07

申请号：US09652216

申请日：2000-08-30

申请人： Tongbi Jiang ,  Zhiqiang Wu

发明人： Tongbi Jiang ,  Zhiqiang Wu

IPC分类号： H05K900

CPC分类号： H01L24/06 ,  H01L23/4827 ,  H01L23/4828 ,  H01L23/585 ,  H01L24/48 ,  H01L27/08 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2223/665 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/8546 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform bias voltage over the substrate. The conductive layer can also be used to apply a bias voltage to the substrate and reduce the number of bias voltage distribution regions required.

摘要翻译： 半导体器件设置有设置在半导体衬底的背面上的导电层。 导电层有助于在衬底上保持均匀的偏置电压。 导电层也可用于向衬底施加偏置电压并减少所需的偏置电压分布区域的数量。

公开(公告)号：US06787839B2

公开(公告)日：2004-09-07

申请号：US10145435

申请日：2002-05-14

申请人： Zhiqiang Wu ,  Kunal Parekh ,  Li Li

发明人： Zhiqiang Wu ,  Kunal Parekh ,  Li Li

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L28/82

摘要： The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.