公开(公告)号：US5528547A

公开(公告)日：1996-06-18

申请号：US332391

申请日：1994-10-31

申请人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

发明人： Seiichi Aritome ,  Riichiro Shirota ,  Ryouhei Kirisawa ,  Yoshihisa Iwata ,  Masaki Momodomi

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C16/16 ,  G11C16/0433 ,  G11C16/0483

摘要： A NAND cell type EEPROM has bit lines, each of which is associated with a NAND cell unit including a series array of four memory cell transistors. Each transistor is a MOSFET with a control gate and a floating gate for data storage. The memory cell transistors are connected at their control gates to word lines, respectively. One end of the NAND cell unit is connected through a first select transistor to a corresponding bit line; the other end thereof is connected via a second select transistor to a source voltage. The memory cell transistors and the select transistors are arranged in a well region formed in a substrate. In an erase mode, the bit line voltage, the substrate voltage and the well voltage are held at a high voltage, whereas the word lines are at zero volts. The gate potential of the select transistors is held at the high voltage, whereby the internal electric field of these select transistors is weakened to improve the dielectric breakdown characteristic thereof.

公开(公告)号：US5392238A

公开(公告)日：1995-02-21

申请号：US226474

申请日：1994-04-11

申请人： Ryouhei Kirisawa

发明人： Ryouhei Kirisawa

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C16/0491 ,  G11C16/0483

摘要： A semiconductor nonvolatile memory device according to the invention comprises a first cell block having with a current path and a plurality of memory cells, a second cell block having with a current path and a plurality of memory cells, the current path of the second cell block has an end connected to a corresponding end of the current path of the first cell block, a first line electrically connected to the other end of the current path of the first cell block, and a second line electrically connected to the other end of the current path of the second cell block. The first and second lines are made to operate a bit line and a source line, or vise versa, depending on which one of said cell blocks is selected for data retrieval.

摘要翻译： 根据本发明的半导体非易失性存储器件包括具有电流路径和多个存储单元的第一单元块，具有电流路径和多个存储单元的第二单元块，第二单元块的当前通路 具有连接到第一单元块的电流路径的对应端的端部，电连接到第一单元块的电流路径的另一端的第一线，以及电连接到电流的另一端的第二线 路径的第二个单元格块。 第一和第二行用于操作位线和源极线，或者反之亦然，取决于选择哪一个所述单元块用于数据检索。

公开(公告)号：US08228737B2

公开(公告)日：2012-07-24

申请号：US12718434

申请日：2010-03-05

申请人： Ryouhei Kirisawa

发明人： Ryouhei Kirisawa

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/0408 ,  H01L27/11565

摘要： A nonvolatile semiconductor memory comprising: a first semiconductor layer having a first stripe-shaped region and a second stripe-shaped region which is adjacent to the first stripe-shaped region; a first NAND string formed on the first stripe-shaped region, the first NAND string having a plurality of first memory cell transistors connected in series; a first insulating film formed above the second stripe-shaped region; a second semiconductor layer formed on the first insulating film; and a second NAND string formed on the second semiconductor layer, the second NAND string having a plurality of second memory cell transistors connected in series.

摘要翻译： 一种非易失性半导体存储器，包括：第一半导体层，具有与所述第一条形区域相邻的第一条形区域和第二条形区域; 形成在所述第一条形区域上的第一NAND串，所述第一NAND串具有串联连接的多个第一存储单元晶体管; 形成在所述第二条形区域上方的第一绝缘膜; 形成在所述第一绝缘膜上的第二半导体层; 以及形成在所述第二半导体层上的第二NAND串，所述第二NAND串具有串联连接的多个第二存储单元晶体管。

公开(公告)号：US5824583A

公开(公告)日：1998-10-20

申请号：US949819

申请日：1997-10-14

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： 本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

公开(公告)号：US5515327A

公开(公告)日：1996-05-07

申请号：US359648

申请日：1994-12-20

申请人： Naohiro Matsukawa ,  Ryouhei Kirisawa ,  Riichiro Shirota

发明人： Naohiro Matsukawa ,  Ryouhei Kirisawa ,  Riichiro Shirota

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C13/00

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： An EEPROM in which a select transistor to which any memory cell not selected is turned off to inhibit electron injections into the floating gate of the memory cell not selected. The memory cells of the EEPROM are arranged in rows and columns in a substrate. The memory cells forming each column are connected in series. The two endmost memory cells are connected to two select transistors, respectively. The bit lines are connected to a data latch/sense amplifier, which is connected to a column decoder. The column decoder controls the bit lines. A row decoder controls select gates and control gates. A voltage-boosting circuit generates a high voltage, which is applied to the substrate and the select gates to erase data in the EEPROM, and to the control gates to write data into the EEPROM. A low-voltage controller generates a low voltage, which is applied to the select gates for turning off the select transistors of the column not selected, thereby to prevent data-writing.

摘要翻译： 一个EEPROM，其中未选择任何存储单元的选择晶体管被截止以禁止未被选择的存储单元的浮动栅极的电子注入。 EEPROM的存储单元以衬底中的行和列排列。 形成每列的存储单元串联连接。 两个最末端的存储单元分别连接到两个选择晶体管。 位线连接到连接到列解码器的数据锁存/读出放大器。 列解码器控制位线。 行解码器控制选择门和控制门。 升压电路产生施加到基板和选择栅极以擦除EEPROM中的数据的高电压，以及向控制栅极写入数据到EEPROM中的高电压。 低电压控制器产生低电压，其施加到选择栅极以关闭未选择的列的选择晶体管，从而防止数据写入。

公开(公告)号：US5508957A

公开(公告)日：1996-04-16

申请号：US312072

申请日：1994-09-26

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

公开(公告)号：US5464998A

公开(公告)日：1995-11-07

申请号：US220590

申请日：1994-03-31

申请人： Toshiyuki Hayakawa ,  Ryouhei Kirisawa

发明人： Toshiyuki Hayakawa ,  Ryouhei Kirisawa

IPC分类号： H01L21/76 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68

CPC分类号： H01L27/115

摘要： A non-volatile semiconductor memory device includes NAND type memory cells arranged in a matrix pattern over a semiconductor substrate and channel stopper layers, provided on the substrate, for separating adjacent NAND type memory cells. Each NAND type memory cell includes memory cell transistors having drains and sources mutually connected in series, a source side select transistor connected to a source of one end transistor of the memory cell transistors, and a drain side select transistor connected to a drain of the other end transistor of the memory cell transistors. Each channel stopper layer has a first layer portion for separating the source side select transistors and a second layer portion for separating the memory cell transistors. Impurity concentration of the first layer portion is lower than that of the second layer portion.

摘要翻译： 非易失性半导体存储器件包括在半导体衬底上以矩阵图案布置的NAND型存储单元和设置在衬底上的用于分离相邻NAND型存储单元的通道阻挡层。 每个NAND型存储单元包括具有串联连接的漏极和源极的存储单元晶体管，连接到存储单元晶体管的一端晶体管的源极的源极侧选择晶体管和连接到另一个漏极的漏极侧选择晶体管 存储单元晶体管的端部晶体管。 每个通道阻挡层具有用于分离源极侧选择晶体管的第一层部分和用于分离存储单元晶体管的第二层部分。 第一层部分的杂质浓度低于第二层部分的杂质浓度。

公开(公告)号：US5440509A

公开(公告)日：1995-08-08

申请号：US22392

申请日：1993-02-24

申请人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Koichi Toita ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba ,  Tetsuo Endo ,  Riichiro Shirota ,  Ryouhei Kirisawa

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115

摘要： An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an "L" level voltage (approximately 0 V) to a word line connected to the selected cell, applying an "H" level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the "H" and "L" level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic "0" data, the intermediate voltage is applied also to the specific bit line.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器（EPROM）包括NAND单元块，每个单元块具有连接到相应位线的选择晶体管和串联连接的存储单元晶体管。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通以将单元块连接到对应的位线。 提供一种控制电路，用于向连接到所选择的单元的字线施加“L”电平电压（大约0V），对位于第一个单元之间的字线或字线施加“H”电平电压（大约20V） 选择字线和连接单元块和与其相关联的特定位线的接触节点，施加与要写入到特定位线的数据相对应的电压，以及在“H”和“L”电平电压之间施加中间电压 到未选择的位线，从而通过隧道将数据写入所选择的单元。 如果数据是逻辑“0”数据，则中间电压也被施加到特定位线。

公开(公告)号：US5397723A

公开(公告)日：1995-03-14

申请号：US728585

申请日：1991-07-11

申请人： Riichiro Shirota ,  Masaki Momodomi ,  Ryozo Nakayama ,  Seiichi Aritome ,  Ryouhei Kirisawa ,  Tetsuro Endoh ,  Shigeyoshi Watanabe

发明人： Riichiro Shirota ,  Masaki Momodomi ,  Ryozo Nakayama ,  Seiichi Aritome ,  Ryouhei Kirisawa ,  Tetsuro Endoh ,  Shigeyoshi Watanabe

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265 ,  H01L21/465

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11517

摘要： A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate. A chosen impurity is doped into the substrate with the insulated gate electrodes serving as a mask to thereby form impurity-doped regions in the substrate.

摘要翻译： 用于形成用作NAND单元型EEPROM的存储单元的FATMOS晶体管阵列的工艺。 多层结构设置在具有由中间绝缘层绝缘的两个层叠导电层的基板上，第一或内部导电层由与基板隔开的第一绝缘层，第二或外部导电层被第二 绝缘层。 蚀刻第二绝缘层以限定蚀刻层部分的第一阵列。 沉积和蚀刻光致抗蚀剂层以限定层部分的第二阵列，每个层部分位于层部分的第一阵列中的两个相邻的层部分之间。 用第一和第二层部分作为掩模蚀刻多层结构，从而在衬底上形成多对绝缘栅电极的阵列。 将所选择的杂质掺杂到衬底中，其中绝缘栅电极用作掩模，从而在衬底中形成杂质掺杂区域。

公开(公告)号：US5323039A

公开(公告)日：1994-06-21

申请号：US499342

申请日：1990-06-21

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： PCT No.PCT / JP89 / 00942 Sec。 371 1990年6月21日第 102（e）日期1990年6月21日PCT提交1989年9月14日PCT公布。 公开号WO90 / 04855 日期为1990年5月3日。本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。