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    Nonvolatile semiconductor memory device having a small number of internal boosting circuits
    1.
    发明授权
    Nonvolatile semiconductor memory device having a small number of internal boosting circuits 失效
    具有少量内部升压电路的非易失性半导体存储器件

    公开(公告)号：US5515327A

    公开(公告)日：1996-05-07

    申请号：US359648

    申请日：1994-12-20

    申请人： Naohiro Matsukawa ,  Ryouhei Kirisawa ,  Riichiro Shirota

    发明人： Naohiro Matsukawa ,  Ryouhei Kirisawa ,  Riichiro Shirota

    IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C13/00

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： An EEPROM in which a select transistor to which any memory cell not selected is turned off to inhibit electron injections into the floating gate of the memory cell not selected. The memory cells of the EEPROM are arranged in rows and columns in a substrate. The memory cells forming each column are connected in series. The two endmost memory cells are connected to two select transistors, respectively. The bit lines are connected to a data latch/sense amplifier, which is connected to a column decoder. The column decoder controls the bit lines. A row decoder controls select gates and control gates. A voltage-boosting circuit generates a high voltage, which is applied to the substrate and the select gates to erase data in the EEPROM, and to the control gates to write data into the EEPROM. A low-voltage controller generates a low voltage, which is applied to the select gates for turning off the select transistors of the column not selected, thereby to prevent data-writing.

    摘要翻译： 一个EEPROM，其中未选择任何存储单元的选择晶体管被截止以禁止未被选择的存储单元的浮动栅极的电子注入。 EEPROM的存储单元以衬底中的行和列排列。 形成每列的存储单元串联连接。 两个最末端的存储单元分别连接到两个选择晶体管。 位线连接到连接到列解码器的数据锁存/读出放大器。 列解码器控制位线。 行解码器控制选择门和控制门。 升压电路产生施加到基板和选择栅极以擦除EEPROM中的数据的高电压，以及向控制栅极写入数据到EEPROM中的高电压。 低电压控制器产生低电压，其施加到选择栅极以关闭未选择的列的选择晶体管，从而防止数据写入。

    Reduced projection type step- and repeat-exposure apparatus
    2.
    发明授权
    Reduced projection type step- and repeat-exposure apparatus 失效
    减少投影型步进和重复曝光装置

    公开(公告)号：US4845530A

    公开(公告)日：1989-07-04

    申请号：US130215

    申请日：1987-12-08

    申请人： Naohiro Matsukawa

    发明人： Naohiro Matsukawa

    IPC分类号： G03F9/00

    CPC分类号： G03F9/70

    摘要： In a reduced projection type step- and repeat-exposure apparatus of the present invention, the angle of inclination of an exposure area on the wafer is first detected, and then corrected on the basis of the detected value. This measurement corrects the inclination of the exposure area. Hence, high precision patterning can be realized, even if an optical system having a small focus margin is used.

    摘要翻译： 在本发明的缩小投射型步进重复曝光装置中，首先检测晶片上的曝光区域的倾斜角度，然后基于检测值进行校正。 此测量可校正曝光区域的倾斜度。 因此，即使使用具有小焦距的光学系统，也可以实现高精度图案化。

    Non-volatile semiconductor memory device capable of preventing excessive-writing
    3.
    发明授权
    Non-volatile semiconductor memory device capable of preventing excessive-writing 失效
    能够防止过度写入的非易失性半导体存储器件

    公开(公告)号：US5559736A

    公开(公告)日：1996-09-24

    申请号：US424646

    申请日：1995-04-19

    申请人： Naohiro Matsukawa ,  Keniti Imamiya ,  Toshiharu Watanabe ,  Michiharu Matsui

    发明人： Naohiro Matsukawa ,  Keniti Imamiya ,  Toshiharu Watanabe ,  Michiharu Matsui

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C16/3413 ,  G11C16/0483 ,  G11C16/3404

    摘要： After data is written into a desired memory cell of a memory cell array, a booster circuit verifies the threshold voltage of the memory cell in which data is written. An erase timing signal generation circuit connected to a control circuit generates a timing signal for a short period of time when a memory cell having a threshold voltage higher than the power supply voltage. An erasing voltage generation circuit applies a negative erasing voltage to the memory cell in which data is written for a short period of time according to the timing signal supplied from the erase timing signal generation circuit to slightly lower the threshold voltage of the memory cell so as to prevent the excessive writing.

    摘要翻译： 在将数据写入存储单元阵列的所需存储单元之后，升压电路验证其中写入数据的存储单元的阈值电压。 连接到控制电路的擦除定时信号产生电路在具有高于电源电压的阈值电压的存储单元的短时间内产生定时信号。 擦除电压产生电路根据从擦除定时信号发生电路提供的定时信号向存储单元施加负的擦除电压，其中数据被写入短时间段，以稍微降低存储器单元的阈值电压，以便 以防止过多的写作。

    Method of manufacturing nonvolatile semiconductor memory device by forming additional impurity doped region under the floating gate
    4.
    发明授权
    Method of manufacturing nonvolatile semiconductor memory device by forming additional impurity doped region under the floating gate 失效
    通过在浮动栅极下形成附加杂质掺杂区域来制造非易失性半导体存储器件的方法

    公开(公告)号：US4642881A

    公开(公告)日：1987-02-17

    申请号：US735211

    申请日：1985-05-17

    申请人： Naohiro Matsukawa ,  Sigeru Morita ,  Hiroshi Nozawa

    发明人： Naohiro Matsukawa ,  Sigeru Morita ,  Hiroshi Nozawa

    IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/788 ,  G11C11/40 ,  H01L21/283

    CPC分类号： H01L29/66825 ,  H01L21/26513 ,  H01L21/28273 ,  H01L29/7883 ,  Y10S148/082

    摘要： A method of manufacturing a nonvolatile semiconductor memory device having a gate oxide layer including a relatively thin silicon dioxide layer. This gate oxide layer including the thin silicon dioxide layer is formed by the steps of forming the gate oxide film on a semiconductor element region in a silicon substrate; removing a portion of the gate oxide film to expose a portion of the silicon substrate; implanting impurity ions in the exposed portion of the substrate to an extent that a peak concentration of the impurity ions exceeds a solid solution limit at a temperature of the following thermal annealing step; activating the implanted impurity by thermal annealing so as to form a high impurity concentration layer and thermally oxidizing a surface of the high impurity concentration layer to form the thin silicon dioxide layer.

    摘要翻译： 一种制造具有包括相对薄的二氧化硅层的栅氧化层的非易失性半导体存储器件的方法。 通过在硅衬底的半导体元件区域上形成栅氧化膜的步骤，形成包括二氧化硅薄层的栅极氧化层; 去除所述栅氧化膜的一部分以暴露所述硅衬底的一部分; 在杂质离子的峰值浓度在随后的热退火步骤的温度下超过固溶极限的程度将杂质离子注入衬底的暴露部分; 通过热退火激活注入的杂质，以便形成高杂质浓度层并热氧化高杂质浓度层的表面以形成薄的二氧化硅层。

    Method for producing a semiconductor device with a floating gate
    5.
    发明授权
    Method for producing a semiconductor device with a floating gate 失效
    用于制造具有浮动栅极的半导体器件的方法

    公开(公告)号：US4620361A

    公开(公告)日：1986-11-04

    申请号：US735059

    申请日：1985-05-17

    申请人： Naohiro Matsukawa ,  Hiroshi Nozawa ,  Shigeru Morita

    发明人： Naohiro Matsukawa ,  Hiroshi Nozawa ,  Shigeru Morita

    IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/76

    CPC分类号： H01L29/66825 ,  H01L27/115

    摘要： A method for producing a semiconductor device comprises a step of forming a first gate insulation layer on a portion of a single crystal silicon substrate and forming a floating gate of polycrystalline silicon on the first gate insulation layer, a step of forming an oxide layer on the exposed portion of the substrate and on the floating gate, and a step of forming a control gate on the floating gate through the oxide layer. In the formation of the oxide layer, a nitride pattern layer is formed on the floating gate, the entire structure is oxidized by using the nitride pattern layer as a mask, thus forming a protective layer on the exposed portion of the substrate, the nitride pattern layer is removed, and the entire structure is again oxidized, thus forming a second gate insulation layer on the floating gate.

    摘要翻译： 一种制造半导体器件的方法包括在单晶硅衬底的一部分上形成第一栅极绝缘层并在第一栅极绝缘层上形成多晶硅浮置栅的步骤，在第一栅极绝缘层上形成氧化物层的步骤 衬底的暴露部分和浮置栅极，以及通过氧化物层在浮置栅极上形成控制栅极的步骤。 在氧化物层的形成中，在浮栅上形成氮化物图案层，通过使用氮化物图案层作为掩模来氧化整个结构，从而在衬底的暴露部分上形成保护层，氮化物图案 层，并且整个结构再次被氧化，从而在浮栅上形成第二栅极绝缘层。

    Memory device resistant to soft errors
    7.
    发明授权
    Memory device resistant to soft errors 失效
    存储器件抵抗软错误

    公开(公告)号：US4592026A

    公开(公告)日：1986-05-27

    申请号：US564683

    申请日：1983-12-23

    申请人： Naohiro Matsukawa ,  Mitsuo Isobe ,  Takayasu Sakurai

    发明人： Naohiro Matsukawa ,  Mitsuo Isobe ,  Takayasu Sakurai

    IPC分类号： G11C11/417 ,  G11C7/12 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C7/12

    摘要： In a memory device, a plurality of memory cells are connected to bit line pairs. A precharge circuit is controlled by a chip enable signal during a stand-by state and by an address transition detector signal during an active state, to charge the bit line pairs up to a given power source voltage.

    摘要翻译： 在存储器件中，多个存储器单元连接到位线对。 在待机状态期间，预充电电路由芯片使能信号和地址转换检测器信号在激活状态期间控制，以将位线对充电至给定的电源电压。

    Semiconductor memory device having tunnel diodes
    8.
    发明授权
    Semiconductor memory device having tunnel diodes 失效
    半导体存储器件具有隧道二极管

    公开(公告)号：US4573143A

    公开(公告)日：1986-02-25

    申请号：US472605

    申请日：1983-03-07

    申请人： Naohiro Matsukawa

    发明人： Naohiro Matsukawa

    IPC分类号： G11C11/38 ,  G11C11/41

    CPC分类号： G11C11/38

    摘要： A semiconductor memory device has at least one memory cell which includes first and second tunnel diodes connected in series in a forward-bias direction between first and second power source terminals. The first and second power source terminals are held at constant potentials. A switching MOS transistor is connected at one end to a connection point between the first and second tunnel diodes. The potential at the connection point between the first and second tunnel diodes is determined by the potential at the other end of the switching MOS transistor.

    摘要翻译： 半导体存储器件具有至少一个存储单元，其包括在第一和第二电源端子之间沿正向偏压方向串联连接的第一和第二隧道二极管。 第一和第二电源端子保持恒定电位。 开关MOS晶体管的一端连接到第一和第二隧道二极管之间的连接点。 在第一和第二隧道二极管之间的连接点处的电位由开关MOS晶体管的另一端的电位决定。

    Nonvolatile semiconductor memory circuit with high speed read-out
    10.
    发明授权
    Nonvolatile semiconductor memory circuit with high speed read-out 失效
    非易失性半导体存储器电路，具有高速读出

    公开(公告)号：US5350938A

    公开(公告)日：1994-09-27

    申请号：US721702

    申请日：1991-06-26

    申请人： Naohiro Matsukawa ,  Junichi Miyamoto

    发明人： Naohiro Matsukawa ,  Junichi Miyamoto

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68

    CPC分类号： H01L27/115

    摘要： A memory cell transistor includes a semiconductor substrate, a N-type source region, a N-type drain region, a control gate and a P.sup.+ -type emitter region, which is formed in the surface region of the drain region. An insulating film overlies the source region, the drain region, the emitter region, and the control gate. A contact hole is formed in the insulating film so that the surface of the emitter region is exposed. An emitter electrode is formed in and around the contact hole. A PNP vertical bipolar transistor is constituted by the semiconductor substrate serving as a collector region, a P.sup.+ -type buried layer serving as a collector contact, and the drain region serving as a base region.

    摘要翻译： 存储单元晶体管包括形成在漏极区域的表面区域中的半导体衬底，N型源极区域，N型漏极区域，控制栅极和P +型发射极区域。 绝缘膜覆盖在源极区域，漏极区域，发射极区域和控制栅极之间。 在绝缘膜中形成接触孔，使得发射极区域的表面露出。 在接触孔内部和周围形成发射电极。 PNP垂直双极晶体管由用作集电极区的半导体衬底，用作集电极接触的P +型掩埋层和用作基极区的漏极区构成。