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197 条记录 (耗时 0.028 秒)

    Optical element
    61.
    发明申请
    Optical element 失效
    光学元件

    公开(公告)号：US20060092498A1

    公开(公告)日：2006-05-04

    申请号：US11062591

    申请日：2005-02-23

    申请人： Keisuke Sato ,  Masao Kondo

    发明人： Keisuke Sato ,  Masao Kondo

    IPC分类号： G02F1/00

    CPC分类号： G02F1/035 ,  G02F1/055

    摘要： An optical waveguide is formed of a stack of electro-optic effect films. A stress-relief layer is formed between a substrate and the optical waveguide. The stress-relief layer is comprised of a metal material having a thermal expansion coefficient of 10×10−6/° C. or higher, for example, a metal material whose major component is one of Au, Ag, and an alloy thereof, and has a function of relieving a binding force to the optical waveguide ascribable to the substrate.

    摘要翻译： 光波导由一组电光效应膜形成。 在基板和光波导之间形成有应力消除层。 应力消除层由热膨胀系数为10×10 -6 /℃以上的金属材料构成，例如主要成分为Au，Ag， 及其合金，具有缓解对归属于基板的光波导的结合力的功能。

    Semiconductor device and manufacturing method of the same
    62.
    发明申请
    Semiconductor device and manufacturing method of the same 失效
    半导体器件及其制造方法相同

    公开(公告)号：US20060073664A1

    公开(公告)日：2006-04-06

    申请号：US11242961

    申请日：2005-10-05

    申请人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

    发明人： Masao Kondo ,  Nobuyuki Sugii ,  Yoshinobu Kimura

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7835 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66659

    摘要： Provided is a technology capable of suppressing a reduction in electron mobility in a channel region formed in a strained silicon layer. A p type strained silicon layer is formed over a p type silicon-germanium layer formed over a semiconductor substrate. The p type strained layer has a thickness adjusted to be thicker than the critical film thickness at which no misfit dislocation occurs. Accordingly, misfit dislocations occur in the vicinity of the interface between the p type strained silicon layer and p type silicon-germanium layer. At a position which is below the end of a gate electrode and at which misfit dislocations occur, the impurity concentration of the n type strained silicon layer and n type silicon-germanium layer is 1×1019 cm−3 or less.

    摘要翻译： 提供了能够抑制形成在应变硅层中的沟道区域中的电子迁移率降低的技术。 在半导体衬底上形成的p型硅 - 锗层上形成p型应变硅层。 p型应变层的厚度被调整为比没有失配位错发生的临界膜厚度更厚。 因此，在p型应变硅层和p型硅 - 锗层之间的界面附近发生失配位错。 在位于栅电极末端并发生失配位错的位置处，n型应变硅层和n型硅 - 锗层的杂质浓度为1×10 19 cm -3， -3以下。

    Optical deflection element and method of producing the same
    65.
    发明申请
    Optical deflection element and method of producing the same 审中-公开
    光偏转元件及其制造方法

    公开(公告)号：US20050162595A1

    公开(公告)日：2005-07-28

    申请号：US11085556

    申请日：2005-03-22

    申请人： Masao Kondo ,  Hideki Yamawaki

    发明人： Masao Kondo ,  Hideki Yamawaki

    IPC分类号： G02F1/055 ,  G02F1/1337 ,  G02F1/295

    CPC分类号： G02F1/055 ,  G02F1/0553 ,  G02F1/295

    摘要： A disclosed optical deflection element includes a magnesia spinel film 22, a lower electrode 23, a lower cladding layer 24, a core layer 25, and an upper cladding layer 26, which are sequentially stacked formed on a silicon single crystal substrate 21. The magnesia spinel film 22, the lower electrode 23, a PLZT film acting as the lower cladding layer 24, and a PZT film acting as the core layer 25 are epitaxially grown on respective underlying layers thereof. Because of a voltage applied between the lower electrode 23 and the upper electrode 26, refractive index variable regions 25A, 24A, in which the refractive index varies, are formed due to the electro-optical effect. Light incident into the core layer 25 is deflected at the interface between the core layer 25 and the refractive index variable regions 25A, 24A to the inner side relative to the surface of the core layer 25.

    摘要翻译： 所公开的光偏转元件包括依次层叠形成在硅单晶基板21上的氧化镁尖晶石膜22，下电极23，下包层24，芯层25和上包层26。 将氧化镁尖晶石膜22，下电极23，作为下包层24的PLZT膜和作为芯层25的PZT膜外延生长在其各自的下层上。 由于电光效应，由于施加在下电极23和上电极26之间的电压，折射率变化的折射率可变区域25A，24A形成。 入射到芯层25的光在芯层25和折射率可变区域25A，24A之间的界面处相对于芯层25的表面向内侧偏转。

    Musical performance data search system
    66.
    发明授权
    Musical performance data search system 有权
    音乐表演数据搜索系统

    公开(公告)号：US06846979B2

    公开(公告)日：2005-01-25

    申请号：US10080357

    申请日：2002-02-20

    申请人： Masao Kondo

    发明人： Masao Kondo

    IPC分类号： G06F17/30 ,  G10H1/00 ,  G10K15/02 ,  G10K15/04 ,  A63H5/00 ,  G04B13/00 ,  G10H7/00

    CPC分类号： G10H1/0041 ,  G10H2240/081 ,  G10H2240/131

    摘要： A search list of records is displayed on a display screen DP. Some records may have the same music title as one item, but are different in other items (genre, rhythm, tempo and the like). A favorite list can be formed by a selection process using a mark FMa (reversible by a favorite switch ST0) on each record. A first or second list can be formed by a search process after a search switch SM5 or ST5 is operated. A desired list is selected by using list selection switches ST1 to ST4 and a desired record is designated by a cursor CR to decide a style. The cursor CR can be moved by one record after another by a normal cursor motion switch SM2 or SM3, and jumped to a record group having different item contents by a special cursor motion switch SM1 or SM4.

    摘要翻译： 记录的搜索列表显示在显示屏DP上。 一些记录可能具有与一个项目相同的音乐标题，但在其他项目（类型，节奏，速度等）中是不同的。 可以通过使用每个记录上的标记FMa（由喜爱的开关ST0可逆）的选择处理来形成最喜爱的列表。 在搜索开关SM5或ST5被操作之后，可以通过搜索处理来形成第一或第二列表。 通过使用列表选择开关ST1至ST4选择期望的列表，并且由光标CR指定期望的记录以确定样式。 光标CR可以由普通光标移动开关SM2或SM3移动一个记录，并通过特殊光标移动开关SM1或SM4跳到具有不同项目内容的记录组。

    Bipolar transistor and manufacturing method thereof
    69.
    发明授权
    Bipolar transistor and manufacturing method thereof 失效
    双极晶体管及其制造方法

    公开(公告)号：US06521974B1

    公开(公告)日：2003-02-18

    申请号：US09689800

    申请日：2000-10-13

    申请人： Katsuya Oda ,  Eiji Ohue ,  Masao Kondo ,  Katsuyoshi Washio ,  Masamichi Tanabe ,  Hiromi Shimamoto

    发明人： Katsuya Oda ,  Eiji Ohue ,  Masao Kondo ,  Katsuyoshi Washio ,  Masamichi Tanabe ,  Hiromi Shimamoto

    IPC分类号： H01L2970

    CPC分类号： H01L29/66287 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

    摘要： A bipolar transistor according to the invention is provided with structure that an intrinsic base made of single crystal Si—Ge and a base leading-out electrode are connected via a link base made of polycrystal Si—Ge by doping at high concentration, further, a part immediately under the intrinsic base has the same conductive type as that of a collector and in a peripheral part, a single crystal Si—Ge layer having the same conductive type as that of a base is provided between the intrinsic base and a collector layer. Hereby, the reduction of the resistance of the link base between the intrinsic base and the base leading-out electrode and the reduction of capacitance between the collector and the base are simultaneously realized, and a self-aligned bipolar transistor wherein capacitance between an emitter and the base and capacitance between the collector and the base are respectively small, power consumption is small and high speed operation is enabled is acquired.

    摘要翻译： 根据本发明的双极晶体管具有以下结构：由单晶Si-Ge构成的本征基极和基极引出电极通过高浓度掺杂的由多晶Si-Ge制成的连接基底连接，此外， 在本征基底之下的部分具有与集电体相同的导电类型，并且在外围部分中，在本征基极和集电极层之间设置具有与基底相同的导电类型的单晶Si-Ge层。 因此，同时实现本征基极与基极引出电极之间的基极的电阻的降低和集电极与基极之间的电容的减小，以及自对准双极晶体管，其中发射极和 集电极和基极之间的基极和电容分别小，功耗小，获得高速运行。

    BICMOS semiconductor integrated circuit device and fabrication process thereof
    70.
    发明授权
    BICMOS semiconductor integrated circuit device and fabrication process thereof 失效
    BICMOS半导体集成电路器件及其制造工艺

    公开(公告)号：US06476450B2

    公开(公告)日：2002-11-05

    申请号：US09808952

    申请日：2001-03-16

    申请人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    发明人： Masao Kondo ,  Katsuyoshi Washio ,  Eiji Oue ,  Hiromi Shimamoto

    IPC分类号： H01L29732

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a BiCOMOS semiconductor integrated circuit device which comprises a semiconductor substrate having an insulating layer internally and partially embedded therein and a semiconductor layer deposited on the insulating layer, an insulated gate type transistor formed in the semiconductor layer, a highly-doped collector layer of a bipolar transistor embedded in an insulating-layer-free portion of the semiconductor substrate, and a low-doped collector layer disposed on the highly-doped collector layer of the bipolar transistor, wherein the height level of the lower portion of the low-doped collector layer is below the height level of the lower portion of the insulating layer so as to attain high breakdown voltage and high speed operation of the bipolar transistor.

    摘要翻译： 本发明提供一种BiCOMOS半导体集成电路器件，其包括半导体衬底，该半导体衬底具有内部并部分地嵌入其中的绝缘层和沉积在绝缘层上的半导体层，形成在半导体层中的绝缘栅型晶体管，高度掺杂的集电极层 嵌入在半导体衬底的绝缘层的部分中的双极晶体管，以及设置在双极晶体管的高掺杂集电极层上的低掺杂集电极层，其中低掺杂量的下部的高度电平 集电极层在绝缘层的下部的高度以下，以获得双极晶体管的高击穿电压和高速工作。