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130 条记录 (耗时 0.038 秒)

    Dynamic random access memory device
    61.
    发明授权
    Dynamic random access memory device 失效
    动态随机存取存储器

    公开(公告)号：US06295241B1

    公开(公告)日：2001-09-25

    申请号：US08251649

    申请日：1994-05-31

    申请人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

    发明人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

    IPC分类号： G11C702

    CPC分类号： G11C11/4091 ,  G11C7/062 ,  G11C7/14 ,  G11C11/4099

    摘要： Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.

    摘要翻译： 这里公开了具有高集成度密度的动态半导体存储器，其具有在基板上形成的并行字线和并行位线。 位线包括一对位线。 存储器单元耦合到字线和位线对的一个位线。 存储单元由亚微米尺寸的MOSFET组成。 读出放大器部分连接到一对位线，并且在数据读出模式下感测和放大一对位线之间的电位差。 放大器部分具有BIMOS结构，具有MOSFET和双极晶体管。 它具有由双极晶体管组成的驱动器部分。

    Nonvolatile semiconductor memory device whose addresses are selected in a multiple access
    64.
    发明授权
    Nonvolatile semiconductor memory device whose addresses are selected in a multiple access 有权
    在多路访问中选择地址的非易失性半导体存储器件

    公开(公告)号：US6097666A

    公开(公告)日：2000-08-01

    申请号：US187021

    申请日：1998-11-06

    申请人： Koji Sakui ,  Kaoru Tokushige ,  Kenichi Imamiya

    发明人： Koji Sakui ,  Kaoru Tokushige ,  Kenichi Imamiya

    IPC分类号： G11C16/02 ,  G11C8/12 ,  G11C16/08 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C8/00

    CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C8/12

    摘要： A block size buffer and block address pre-decoder are provided for a flash memory. At the time of data erase, the size of a block to be erased is input to the block size buffer and a set of block addresses is input to the block address pre-decoder. An output signal of the block size buffer is supplied to and decoded by the block address pre-decoder, a row decoder is controlled based on the result of pre-decoding, and a plurality of addressing including the above block address as a top address are selected in a multiple manner. Then, a plurality of successive blocks are simultaneously selected to simultaneously erase data in the memory cells in the plurality of blocks.

    摘要翻译： 为闪存提供块大小缓冲器和块地址预解码器。 在数据擦除时，要擦除的块的大小被输入到块大小缓冲器，并且一组块地址被输入到块地址预解码器。 块大小缓冲器的输出信号被提供给块地址预解码器并由块地址预解码器解码，基于预解码的结果控制行解码器，并且包括作为顶部地址的上述块地址的多个寻址是 以多种方式选择。 然后，同时选择多个连续的块，以同时擦除多个块中的存储单元中的数据。

    Semiconductor memory device
    65.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5517457A

    公开(公告)日：1996-05-14

    申请号：US360289

    申请日：1994-12-21

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Non-volatile semiconductor memory device
    66.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5453955A

    公开(公告)日：1995-09-26

    申请号：US255904

    申请日：1994-06-07

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Masaki Momodomi ,  Riichiro Shirota ,  Fujio Masuoka

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Masaki Momodomi ,  Riichiro Shirota ,  Fujio Masuoka

    IPC分类号： G11C16/02 ,  G11C7/12 ,  G11C16/06 ,  G11C16/26 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C16/26

    摘要： A non-volatile semiconductor memory device includes read charging transistors for setting bit lines at a predetermined read potential to perform a data read operation, and read discharging transistors for setting non-selected bit lines at the ground potential during the read operation. These transistors are controlled by different control signals, obtained by detecting an address change, for every other bit line in accordance with an input address so that the read discharging transistors are kept ON to set the non-selected bit lines at the ground potential before and during the data read operation.

    摘要翻译： 非挥发性半导体存储器件包括用于将位线设置在预定读取电位以执行数据读取操作的读取充电晶体管，并且在读取操作期间读取用于将未选择的位线设置为接地电位的放电晶体管。 这些晶体管由不同的控制信号控制，通过根据输入地址对每隔一个位线检测地址变化而获得，使得读出的放电晶体管保持导通，以将未选择的位线设置在地电位之前， 在数据读取操作期间。

    Semiconductor vertical MOSFET inverter circuit
    67.
    发明授权
    Semiconductor vertical MOSFET inverter circuit 失效
    半导体垂直MOSFET逆变电路

    公开(公告)号：US5311050A

    公开(公告)日：1994-05-10

    申请号：US796602

    申请日：1991-11-22

    申请人： Akihiro Nitayama ,  Koji Sakui

    发明人： Akihiro Nitayama ,  Koji Sakui

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L27/092 ,  H01L29/4236

    摘要： A semiconductor device including a semiconductor substrate 1 and at least one first column-shaped semiconductor layer 10 of a first channel type formed on semiconductor substrate 1 in order of first, second and third regions, and having a side surface. At least one second column-shaped semiconductor layer 11 of a second channel type is selectively laminated on first semiconductor layer 10 in order of first, second and third regions, and having a side surface. A gate insulation film 8 is formed on the side surfaces of first semiconductor layer 10 and second semiconductor layer 11. A gate electrode 9 is formed on the insulation film 8 extending to an external portion of first semiconductor layer 10. A first source layer 2 and first drain layer 4 are respectively formed in the first and third regions of first semiconductor layer 10. A second source layer 7 and second drain layer 5 are respectively formed in the first and third regions of semiconductor layer 11. An input terminal 14 is connected to gate electrode 9 to lead out to the exterior of first semiconductor layer 10. An output terminal 15 is connected to second drain layer 5 formed on and in low-resistance contact with first drain layer. A first power source terminal 16 is connected to first source layer 2 of first semiconductor layer 10, and a second power source terminal 17 is connected to second source layer 7.

    摘要翻译： 一种半导体器件，包括半导体衬底1和形成在半导体衬底1上的第一沟道型的至少一个第一柱状半导体层10，其具有第一，第二和第三区域的顺序并且具有侧表面。 第二沟道型的至少一个第二列状半导体层11按照第一，第二和第三区域的顺序选择性层压在第一半导体层10上，并具有侧面。 在第一半导体层10和第二半导体层11的侧表面上形成栅极绝缘膜8.在延伸到第一半导体层10的外部的绝缘膜8上形成栅电极9.第一源极层2和 第一漏极层4分别形成在第一半导体层10的第一和第三区域中。第二源极层7和第二漏极层5分别形成在半导体层11的第一和第三区域中。输入端子14连接到 栅极电极9引出到第一半导体层10的外部。输出端子15连接到形成在第一漏极层上并与第一漏极层低电阻接触的第二漏极层5。 第一电源端子16连接到第一半导体层10的第一源极层2，第二电源端子17连接到第二源极层7。

    Divided bit line type dynamic random access memory with charging/discharging current suppressor
    69.
    发明授权
    Divided bit line type dynamic random access memory with charging/discharging current suppressor 失效
    具有充电/放电电流抑制器的分立位线型动态随机存取存储器

    公开(公告)号：US4926382A

    公开(公告)日：1990-05-15

    申请号：US275395

    申请日：1988-11-23

    申请人： Koji Sakui ,  Kazunori Ohuchi ,  Fujio Masuoka

    发明人： Koji Sakui ,  Kazunori Ohuchi ,  Fujio Masuoka

    IPC分类号： G11C11/401 ,  G11C11/4097

    CPC分类号： G11C11/4097

    摘要： A divided bit line type dynamic semiconductor memory device comprises parallel main bit line pairs, divided bit line pairs provided at each main bit line pair, parallel word lines insulatively crossing the divided bit line pairs, and memory cells provided at the cross points between the divided bit line pairs and the word lines. First sense amplifiers are coupled to the divided bit line pairs. Second sense amplifiers are coupled to the main bit line pairs. First transfer gate sections are coupled between the divided bit line pairs and the main bit line pairs, respectively. Second transfer gate sections are coupled between the main bit line pairs and the second sense amplifier circuits, respectively. A charging/discharging current suppressor is provided which, in both of the read and restoring modes, restricts the amplitude of the potential change, due to charging/discharging, of a specifi main bit line pair associated with a selected divided bit line pair including a selected cell to be smaller than a full potential change defined by the source voltage and ground potential of the device, whereby a charging/discharging cuffent flowing through the specific main bit line pair is reduced so that the dissipation power of the dRAM is saved and its operation speed is improved.

    摘要翻译： 分割位线型动态半导体存储器件包括并行主位线对，在每个主位线对上设置的分开的位线对，与划分的位线对绝对地交叉的并行字线，以及设置在分割的位线对之间的交叉点处的存储单元 位线对和字线。 第一读出放大器耦合到分开的位线对。 第二读出放大器耦合到主位线对。 第一传输门部分分别耦合在分开的位线对和主位线对之间。 第二传输门部分分别耦合在主位线对和第二读出放大器电路之间。 提供了一种充电/放电电流抑制器，其在读取和恢复模式中都限制与所选择的分割位线对相关联的特定位线对的由于充电/放电引起的电位变化的幅度，包括 所选择的电池小于由器件的源极电压和接地电位限定的全部电位变化，从而减小流过特定主位线对的充电/放电脉冲，从而节省dRAM的耗散功率， 操作速度提高。

    Semiconductor integrated circuit device
    70.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US4780854A

    公开(公告)日：1988-10-25

    申请号：US878691

    申请日：1986-06-26

    申请人： Yohji Watanabe ,  Hiroshi Ikeda ,  Koji Sakui

    发明人： Yohji Watanabe ,  Hiroshi Ikeda ,  Koji Sakui

    IPC分类号： H01L27/04 ,  G05F3/24 ,  G11C11/407 ,  H01L21/822 ,  H02M3/155 ,  G11C7/00

    CPC分类号： H02M3/155

    摘要： A semiconductor integrated circuit device including a power supply voltage converter and internal circuits. The converter converts an external power supply voltage to an internal power supply voltage of a predetermined value. The internal circuits are driven by the internal power supply voltage. The internal circuits include a clock generator. The converter comprises a reference voltage generator, an output circuit for lowering the external power supply voltage, thereby outputting the internal power supply voltage, and an error signal amplifier for comparing the internal power supply voltage with the reference voltage generated by the reference voltage generator and for controlling the conductance of the output circuit to make the compared voltages equal. The error signal amplifier includes a control signal generator for generating control signals in response to the clock pulses output by the clock generator, and a current control circuit for changing, in accordance with the control signals, the current supplied from an external power supply to the error signal amplifier.

    摘要翻译： 一种包括电源电压转换器和内部电路的半导体集成电路器件。 该转换器将外部电源电压转换为预定值的内部电源电压。 内部电路由内部电源电压驱动。 内部电路包括时钟发生器。 转换器包括参考电压发生器，用于降低外部电源电压的输出电路，从而输出内部电源电压;以及误差信号放大器，用于将内部电源电压与由参考电压发生器产生的参考电压和 用于控制输出电路的电导，使比较的电压相等。 误差信号放大器包括：控制信号发生器，用于响应于由时钟发生器输出的时钟脉冲产生控制信号;以及电流控制电路，用于根据控制信号将从外部电源提供的电流改变为 误差信号放大器。