公开(公告)号：US07924060B2

公开(公告)日：2011-04-12

申请号：US12347446

申请日：2008-12-31

Applicant: Chang-Kyu Choi ,  Kyung-Hoon Kim

Inventor： Chang-Kyu Choi ,  Kyung-Hoon Kim

IPC: H03K19/20

CPC classification number: H03K5/08 ,  H04L25/0264 ,  H04L25/028

Abstract: An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

Abstract translation: 半导体器件的输出电路包括：信号选择器，被配置为接收第一和第二输入数据信号，并响应于相位信号顺序地输出第一和第二输入数据信号; 以及输出电平控制器，被配置为基于第一和第二输入数据信号来控制信号选择器的输出信号的电压电平。

公开(公告)号：US20100308860A1

公开(公告)日：2010-12-09

申请号：US12494433

申请日：2009-06-30

Applicant: Kyung-Hoon Kim ,  Sang-Sic Yoon

Inventor： Kyung-Hoon Kim ,  Sang-Sic Yoon

IPC: H03K17/16 ,  H03K19/0175

CPC classification number: H03K17/164 ,  H03K17/167

Abstract: A semiconductor device includes a plurality of data driving units, each configured to drive a corresponding data output pad by a power supply voltage supplied through a power supply voltage input pin and a ground voltage supplied through a ground voltage input pin, in response to a corresponding bit of a data code, a pattern sensing unit configured to sense a bit pattern of the data code and generate a pattern sensing signal, and a phantom driving unit configured to form a current path between the power supply voltage input pin and the ground voltage input pin and to drive the current path by a driving force determined in response to the pattern sensing signal.

Abstract translation: 半导体器件包括多个数据驱动单元，每个数据驱动单元被配置为响应于相应的数据驱动单元，通过由电源电压输入引脚提供的电源电压和通过接地电压输入引脚提供的接地电压来驱动对应的数据输出焊盘 数据代码的位;模式感测单元，被配置为感测数据代码的位模式并生成模式感测信号;以及幻影驱动单元，被配置为在电源电压输入引脚和接地电压输入之间形成电流路径 并且通过响应于图案感测信号确定的驱动力来驱动电流路径。

公开(公告)号：US07848178B2

公开(公告)日：2010-12-07

申请号：US12006121

申请日：2007-12-31

Applicant: Kyung-Hoon Kim ,  Sang-Sik Yoon

Inventor： Kyung-Hoon Kim ,  Sang-Sik Yoon

IPC: G11C8/00

CPC classification number: G11C8/18 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

Abstract: Semiconductor memory device and method for operating the same includes a phase detection unit configured to compare a phase of a first reference clock and a phase of a second divided reference clock to output a comparison result signal and a phase control and division unit configured to generate the second divided reference clock by dividing a second reference clock by a predetermined ratio according to the comparison result signal outputted from the phase detection unit and adjusting a phase of the second reference clock.

Abstract translation: 半导体存储器件及其操作方法包括：相位检测单元，被配置为比较第一参考时钟的相位和第二分频基准时钟的相位，以输出比较结果信号;相位控制和分频单元，被配置为产生 根据从相位检测单元输出的比较结果信号，将第二参考时钟除以预定比例，并调整第二参考时钟的相位，来分配第二分频参考时钟。

公开(公告)号：US07834611B2

公开(公告)日：2010-11-16

申请号：US12266693

申请日：2008-11-07

Applicant: Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

Inventor： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC: G05F3/16 ,  G05F1/10

CPC classification number: G05F3/30 ,  G11C5/147

Abstract: A bandgap reference generating circuit includes an operational amplifier configured to generate a bandgap reference voltage; and a gain controller configured to control a gain of the operational amplifier with different values in a normal mode and a low power mode.

Abstract translation: 带隙参考产生电路包括：运算放大器，被配置为产生带隙参考电压; 以及增益控制器，被配置为在正常模式和低功率模式下以不同的值来控制运算放大器的增益。

公开(公告)号：US07816941B2

公开(公告)日：2010-10-19

申请号：US12215830

申请日：2008-06-30

Applicant: Kyung-Whan Kim ,  Kyung-Hoon Kim

Inventor： Kyung-Whan Kim ,  Kyung-Hoon Kim

IPC: H03K17/16 ,  H03K19/003 ,  G11C7/00

CPC classification number: G11C5/063 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/2254

Abstract: A termination impedance control circuit is capable of controlling a dynamic ODT operation in a DDR3-level semiconductor memory device. The termination impedance control circuit includes a counter unit configured to count an external clock and an internal clock to output a first code and a second code, respectively, and a dynamic controller configured to enable a dynamic termination operation by comparing the first code with the second code in response to a write command and disable the dynamic termination operation after a predetermined time, determined according to a burst length, has lapsed after the dynamic termination operation is enabled.

Abstract translation: 终端阻抗控制电路能够控制DDR3级半导体存储器件中的动态ODT操作。 终端阻抗控制电路包括：计数器单元，被配置为对外部时钟和内部时钟进行计数，以分别输出第一代码和第二代码;以及动态控制器，被配置为通过将第一代码与第二代码进行比较来实现动态终止操作 响应于写命令的代码，并且在启用了动态终止操作之后已经经过了在根据突发长度确定的预定时间之后禁用动态终止操作。

公开(公告)号：US07812650B2

公开(公告)日：2010-10-12

申请号：US12157235

申请日：2008-06-09

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC: H03L7/06

CPC classification number: H03L7/0893 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06

Abstract: Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

Abstract translation: 偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元，被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元 以接收放大单元的输出信号以输出偏置电压。

公开(公告)号：US20100164572A1

公开(公告)日：2010-07-01

申请号：US12486320

申请日：2009-06-17

Applicant: Kyung-Hoon Kim

Inventor： Kyung-Hoon Kim

IPC: H03L7/06 ,  H03L7/00

CPC classification number: H03L7/0814 ,  G11C7/1045 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

Abstract: A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.

Abstract translation: 一种半导体器件包括等待时间信号发生电路，用于通过测量在延迟锁定环路处反映的延迟量并反映读取命令信号的测量延迟量来产生对应于CAS等待时间的等待时间信号，以及延迟锁定环路，用于控制内部时钟 信号被施加到对应于读命令和等待时间信号的等待时间信号发生电路。 半导体器件包括：内部时钟信号产生模块，用于产生内部时钟信号;等待时间产生模块，被配置为通过在与CAS等待时间值对应的时间同步读取命令信号和内部时钟信号来生成等待时间信号; 测量延迟值，以及输入控制块，被配置为响应于读取命令信号和等待时间信号，使用外部时钟信号激活参考时钟信号。

公开(公告)号：US07688813B2

公开(公告)日：2010-03-30

申请号：US11286891

申请日：2005-11-22

Applicant: Sang-Cheol Shin ,  Kyung-Hoon Kim ,  Jong-Cheol Jung ,  Young-Ho Jung

Inventor： Sang-Cheol Shin ,  Kyung-Hoon Kim ,  Jong-Cheol Jung ,  Young-Ho Jung

IPC: H04L12/50

CPC classification number: H04L67/025 ,  H04L67/02 ,  H04L67/04 ,  H04L67/125

Abstract: Disclosed is a monitoring control system and method that can minimize network delay between a local side PC and a phone side PC when monitoring a mobile communication device in real time. By consecutively sending a plurality of monitoring requests for monitoring the mobile communication device via the Internet, monitoring the mobile communication device and consecutively receiving a plurality of monitoring results corresponding to the plurality of monitoring requests via the Internet, real time monitoring of the mobile communication device is facilitated with minimized delay.

Abstract translation: 公开了一种监视控制系统和方法，其可以在实时监视移动通信设备时最小化本地侧PC和电话侧PC之间的网络延迟。 通过经由因特网连续发送多个用于监视移动通信装置的监视请求，监视移动通信装置，并经由因特网连续地接收对应于多个监视请求的多个监视结果，对移动通信装置 以最小的延迟方便。

公开(公告)号：US20090160560A1

公开(公告)日：2009-06-25

申请号：US12079443

申请日：2008-03-26

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC: H03L7/00

CPC classification number: H03L7/0893 ,  H03L7/0896 ,  H03L7/0898

Abstract: Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump.

Abstract translation: 锁相环及其控制方法包括相位/频率检测器，被配置为检测输入时钟和反馈时钟之间的相位差，以根据检测到的相位差产生上升信号或下降信号，电荷泵被配置为 根据其中输入的带宽控制信号可变地控制带宽，所述电荷泵响应于上升信号或下降信号而工作;以及压控振荡器，被配置为根据电荷泵的输出来改变频率。

公开(公告)号：US20090160510A1

公开(公告)日：2009-06-25

申请号：US12157235

申请日：2008-06-09

Applicant: Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

Inventor： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC: H03L7/06 ,  H03K3/01

CPC classification number: H03L7/0893 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06

Abstract: Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

Abstract translation: 偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元，被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元 以接收放大单元的输出信号以输出偏置电压。