公开(公告)号：US07282403B2

公开(公告)日：2007-10-16

申请号：US11203952

申请日：2005-08-15

申请人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

发明人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

公开(公告)号：US20070063278A1

公开(公告)日：2007-03-22

申请号：US11162780

申请日：2005-09-22

申请人： Bruce Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

发明人： Bruce Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

IPC分类号： H01L27/12

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903 ,  Y10S438/973

摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

摘要翻译： 本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。 这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。 下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。 衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。 更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于 传输栅晶体管。

公开(公告)号：US07176116B2

公开(公告)日：2007-02-13

申请号：US11074223

申请日：2005-03-07

申请人： Cyril Cabral, Jr. ,  Omer H. Dokumaci ,  Oleg Gluschenkov

发明人： Cyril Cabral, Jr. ,  Omer H. Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7836

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET在器件沟道上方具有器件沟道和栅极，在薄沟道的每个端部具有掺杂的源极/漏极延伸。 低电阻材料层（例如硅化物层）的一部分设置在源极/漏极延伸部分上。 掺杂延伸部分上的部分横向形成与掺杂源极/漏极延伸部的直接接触。 栅极上的任何低电阻材料层与源极/漏极延伸部分上的低电阻材料部分分离。

公开(公告)号：US20060234398A1

公开(公告)日：2006-10-19

申请号：US10907798

申请日：2005-04-15

申请人： Oleg Gluschenkov ,  Timothy Little ,  Gary Snyder

发明人： Oleg Gluschenkov ,  Timothy Little ,  Gary Snyder

IPC分类号： H01L21/00 ,  H01L21/66 ,  H01L21/306 ,  B05C11/00

CPC分类号： H01L21/67294

摘要： An apparatus and method for real-time monitoring process conditions of a semiconductor wafer processing operation. A semiconductor wafer subject to processing in a wafer processing tool is embedded with one or more sensor devices. In response to receipt of wireless electromagnetic signals, the embedded sensor devices are activated for generating sensory data. The electromagnetic signals are further utilized to activate a transmitter device provided in the wafer to wirelessly transmit the sensory data generated from the activated embedded sensor device. The transmitted electromagnetic signals comprising the sensory data are communicated to a control device for controlling processing conditions of the process tool based upon the received sensory data.

摘要翻译： 一种用于实时监测半导体晶片处理操作的工艺条件的装置和方法。 在晶片处理工具中进行处理的半导体晶片被嵌入一个或多个传感器装置。 响应于接收到无线电磁信号，嵌入式传感器装置被激活以产生感觉数据。 进一步利用电磁信号来激活设置在晶片中的发射器装置，以无线地传输由激活的嵌入式传感器装置产生的感觉数据。 包含感官数据的发送的电磁信号被传送到控制装置，用于基于所接收的感觉数据来控制处理工具的处理条件。

公开(公告)号：US20060223290A1

公开(公告)日：2006-10-05

申请号：US10907454

申请日：2005-04-01

申请人： Michael Belyansky ,  Oleg Gluschenkov ,  Ying Li ,  Anupama Mallikarjunan

发明人： Michael Belyansky ,  Oleg Gluschenkov ,  Ying Li ,  Anupama Mallikarjunan

IPC分类号： H01L21/265 ,  H01L21/31

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface of a substrate, said first portion having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified such that the first state of mechanical strain is not substantially altered, while increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times to obtain a preselected and desired thickness for the stressor.

摘要翻译： 提供了通过改变这种压力源的内部结构来增加非晶薄膜应力的应力水平的方法。 该方法包括首先在基底的至少一个表面上形成非晶膜应力材料的第一部分，所述第一部分具有限定第一应力值的第一机械应变状态。 在成形步骤之后，非晶态应力材料的第一部分被致密化，使得在增加第一应力值的同时，基本上不改变机械应变的第一状态。 在一些实施例中，形成和致密化的步骤重复任意次数，以获得应激源的预选和期望的厚度。

公开(公告)号：US07030012B2

公开(公告)日：2006-04-18

申请号：US10708530

申请日：2004-03-10

申请人： Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

发明人： Ramachandra Divakaruni ,  Oleg Gluschenkov ,  Oh-Jung Kwon ,  Rajeev Malik

IPC分类号： H01L21/44

CPC分类号： H01L27/10894 ,  H01L27/10861 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device including at least one semiconductor memory array region and logic circuits including a support region is formed by the following steps. Form a sacrificial polysilicon layer over the array region. Form a blanket gate oxide layer over the device. Form a thick deposit of polysilicon in both the array region where word lines are located and in the support region where the logic circuits are located. Remove the thick polysilicon layer, the gate oxide layer and the sacrificial polysilicon layer only in the array region. Then deposit a thin polysilicon layer in both the array region and support regions. Next deposit a metallic conductor coating including at least an elemental metal layer portion over the thin polysilicon layer. Then form word lines and sate electrodes in the array region and support region respectively.

摘要翻译： 包括至少一个半导体存储器阵列区域和包括支撑区域的逻辑电路的集成电路器件通过以下步骤形成。 在阵列区域上形成牺牲多晶硅层。 在器件上形成覆盖栅极氧化物层。 在字线位于的阵列区域和逻辑电路所在的支撑区域中形成厚多晶硅沉积物。 仅在阵列区域中去除厚的多晶硅层，栅极氧化物层和牺牲多晶硅层。 然后在阵列区域和支撑区域中沉积薄多晶硅层。 接着在薄多晶硅层上沉积至少包含元素金属层部分的金属导体涂层。 然后分别在阵列区域和支撑区域中形成字线和基极。

公开(公告)号：US07023041B2

公开(公告)日：2006-04-04

申请号：US10341187

申请日：2003-01-13

申请人： Giuseppe La Rosa ,  Thomas W. Dyer ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens ,  Alvin W. Strong

发明人： Giuseppe La Rosa ,  Thomas W. Dyer ,  Oleg Gluschenkov ,  Jack A. Mandelman ,  Carl J. Radens ,  Alvin W. Strong

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L29/945 ,  H01L27/10861 ,  H01L27/10894 ,  H01L29/66181

摘要： A versatile structure is formed, based on a deep trench, vertical transistor DRAM cell, that forms a conductive extension of the trench electrode in an elongated trench that contacts the lower electrode of the vertical transistor. The structure can be used as a capacitor, as a discrete transistor as a single-transistor amplifier or as a building block for more complex circuits.

摘要翻译： 基于深沟槽垂直晶体管DRAM单元形成通用结构，其在与垂直晶体管的下电极接触的细长沟槽中形成沟槽电极的导电延伸。 该结构可以用作电容器，作为单晶体管放大器的分立晶体管或作为更复杂电路的构建块。

公开(公告)号：US07002209B2

公开(公告)日：2006-02-21

申请号：US10851830

申请日：2004-05-21

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

摘要翻译： 本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力 。 在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。 本发明还提供了形成上述半导体器件的方法。

公开(公告)号：US20060001162A1

公开(公告)日：2006-01-05

申请号：US11084724

申请日：2005-03-18

申请人： Ronald Schutz ,  Werner Robl ,  Rajeev Malik ,  Lawrence Clevenger ,  Oleg Gluschenkov ,  Cyril Cabral ,  Roy Iggulden ,  Yun-Yu Wang ,  Keith Wong ,  Irene McStay

发明人： Ronald Schutz ,  Werner Robl ,  Rajeev Malik ,  Lawrence Clevenger ,  Oleg Gluschenkov ,  Cyril Cabral ,  Roy Iggulden ,  Yun-Yu Wang ,  Keith Wong ,  Irene McStay

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/7685 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/76838 ,  H01L21/76855 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L2221/1078

摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.

摘要翻译： 提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34） 并且在氮化钨层上形成钨层。 该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。 该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

公开(公告)号：US06977194B2

公开(公告)日：2005-12-20

申请号：US10695752

申请日：2003-10-30

申请人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov

发明人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov

IPC分类号： H01L21/20 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L21/44 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/72 ,  H01L29/78 ,  H01L29/786 ,  H01L31/062

CPC分类号： H01L29/7845 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785

摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

摘要翻译： 在制造包括nFET和pFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。 在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。 通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。