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公开(公告)号:US20250023829A1
公开(公告)日:2025-01-16
申请号:US18903040
申请日:2024-10-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Yamin Friedman , Idan Burstein , Ariel Shahar , Roee Moyal , Gil Kremer
IPC: H04L47/62 , H04L47/6275 , H04L49/90
Abstract: An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.
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62.
公开(公告)号:US12182394B2
公开(公告)日:2024-12-31
申请号:US17658292
申请日:2022-04-07
Applicant: Mellanox Technologies, Ltd.
Inventor: Yamin Friedman , Idan Burstein , Gal Yefet
IPC: G06F3/06
Abstract: A method and system are provided for limiting unnecessary data traffic on the data communication connections connecting various system components, including the various levels of system memory. Some embodiments may include processing a buffer allotment request and/or a buffer release command in coordination with a system or network operation requiring temporary storage of data in a memory buffer. The buffer allotment request may be capable of indicating the amount of storage space required on the memory buffer to execute the system or network operation. The system may be capable of precluding the system or network operation from executing until there is sufficient space in the memory buffer to complete the operation without evicting operational data from the memory buffer. In some embodiments, the buffer release command may signal completion of the system or network operation and release of the utilized memory buffer space for other operations.
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公开(公告)号:US20240340197A1
公开(公告)日:2024-10-10
申请号:US18744636
申请日:2024-06-16
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Daniel Marcovitch , Idan Burstein , Liran Liss , Hillel Chapman , Dror Goldenberg , Michael Kagan , Aviad Yehezkel , Peter Paneah
IPC: H04L12/46 , G06F13/40 , G06F13/42 , G06F15/173
CPC classification number: H04L12/4625 , G06F13/4027 , G06F13/4208 , G06F15/17331 , H04L12/4633 , G06F2213/0026
Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
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公开(公告)号:US20240171520A1
公开(公告)日:2024-05-23
申请号:US17990768
申请日:2022-11-21
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Yamin Friedman , Idan Burstein , Ariel Shahar , Roee Moyal , Gil Kremer
IPC: H04L47/62 , H04L47/6275 , H04L49/90
CPC classification number: H04L47/624 , H04L47/6275 , H04L49/9036
Abstract: An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.
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公开(公告)号:US20240080266A1
公开(公告)日:2024-03-07
申请号:US17902920
申请日:2022-09-05
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Yamin Friedman , Omer Shabtai , Rotem Levinson , Idan Burstein , Yuval Shpigelman , Charlie Mbariky
CPC classification number: H04L45/38 , H04L45/24 , H04L45/566
Abstract: A network adapter includes a port and one or more circuits. The port communicates packets over a network in which switches forward packets in accordance with tuples of the packets. The one or more circuits are to hold a user-programmable scheme specifying assignments of the packets of a given flow destined to a peer node to sub-flows having respective different tuples, assign first packets of the given flow to one or more of the sub-flows in accordance with the user-programmable scheme, by setting respective tuples of the first packets, transmit the first packets to the peer node via the port, monitor notifications received from the network, the notifications being indicative of respective states of the sub-flows, based on the notifications and on the user-programmable scheme determine an assignment of second packets of the given flow to the sub-flows, and transmit the second packets to the peer node via the port.
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66.
公开(公告)号:US11914865B2
公开(公告)日:2024-02-27
申请号:US17658679
申请日:2022-04-11
Applicant: Mellanox Technologies, Ltd.
Inventor: Yamin Friedman , Idan Burstein , Hillel Chapman , Gal Yefet
IPC: G06F3/06 , G06F12/06 , G06F12/08 , G06F12/0897
CPC classification number: G06F3/0613 , G06F3/0652 , G06F3/0659 , G06F3/0673 , G06F12/06 , G06F12/0897
Abstract: A method and system are provided for limiting unnecessary data traffic on the data busses connecting the various levels of system memory. Some embodiments may include processing an invalidation command associated with a system or network operation requiring temporary storage of data in a local memory area. The invalidation command may comprise a memory location indicator capable of identifying the physical addresses of the associated data in the local memory area. Some embodiments may preclude the data associated with the system or network operation from being written to a main memory by invalidating the memory locations holding the temporary data once the system or network operation has finished utilizing the local memory area.
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公开(公告)号:US11909856B2
公开(公告)日:2024-02-20
申请号:US18076423
申请日:2022-12-07
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Miriam Menes , Noam Bloch , Adi Menachem , Idan Burstein , Ariel Shahar , Maxim Fudim
CPC classification number: H04L9/0625 , H04L9/0861 , H04L9/3247
Abstract: In one embodiment, an apparatus includes a network interface to receive a sequence of data packets from a remote device responsively to a data transfer request, the received sequence including received data blocks, and packet processing circuitry to read cryptographic parameters from a memory in which the parameters were registered by a processing unit, the cryptographic parameters including an initial cryptographic key and initial value, compute a first cryptographic key responsively to the initial cryptographic key and initial value, cryptographically process a first block responsively to the first cryptographic key, compute an updated value responsively to the initial value and a size of the first block, compute a second cryptographic key responsively to the initial cryptographic key and the updated value, cryptographically process a second block of the received data blocks responsively to the second cryptographic key, and write the cryptographically processed first and second block to the memory.
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公开(公告)号:US20240039849A1
公开(公告)日:2024-02-01
申请号:US17875999
申请日:2022-07-28
Applicant: Mellanox Technologies, Ltd.
Inventor: Michael Weiner , Avi Urman , Gary Mataev , Idan Burstein
IPC: H04L47/125 , H04W28/08 , H04L47/32
CPC classification number: H04L47/125 , H04W28/08 , H04L47/32
Abstract: Methods, systems, and computer program products for selecting packing processing cores are provided. An example system includes a plurality of packet processing cores and a load balancing unit communicatively connected to the plurality of packet processing cores. The load balancing unit is configured to receive a workflow packet including packet description data indicative of at least a packet structure and a packet priority and receive, from the plurality of packet processing cores, state data indicative of at least a utilization state and an operating state of each of the respective packet processing cores. The load balancing unit determines a selected packet processing core from amongst the plurality of packet processing cores based on the state data of the packet processing core and the packet description data of the workflow packet and transmits the workflow packet to the selected packet processing core.
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公开(公告)号:US11750418B2
公开(公告)日:2023-09-05
申请号:US17013677
申请日:2020-09-07
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Daniel Marcovitch , Idan Burstein , Liran Liss , Hillel Chapman , Dror Goldenberg , Michael Kagan , Aviad Yehezkel , Peter Paneah
IPC: H04L12/46 , G06F13/40 , G06F13/42 , G06F15/173
CPC classification number: H04L12/4625 , G06F13/4027 , G06F13/4208 , G06F15/17331 , H04L12/4633 , G06F2213/0026
Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
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公开(公告)号:US11622004B1
公开(公告)日:2023-04-04
申请号:US17890385
申请日:2022-08-18
Applicant: Mellanox Technologies, Ltd.
Inventor: Yamin Friedman , Idan Burstein , Ariel Shahar , Diego Crupnicoff , Roee Moyal
IPC: H04L67/1097
Abstract: A method for communication includes receiving in a network device work requests posted by a host processor to perform a series of communication transactions, including at least a first transaction and a second transaction comprising first and second operations to be executed in a sequential order in response to corresponding first and work requests posted by the host processor. In response to the work requests, data packets are transmitted over a network from the network device to a destination node and corresponding responses are received from the destination node. Based on the received responses, completion of the first operations in the first transaction is reported from the network device to the host processor according to the sequential order, and completion of the second operation in the second transaction is reported from the network device to the host processor regardless of whether the first transaction has been completed.
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