公开(公告)号：US12255163B2

公开(公告)日：2025-03-18

申请号：US17666437

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Keizo Kawakita ,  Bret K. Street

IPC: H01L23/00 ,  H01L25/065

Abstract: Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.

公开(公告)号：US20250079366A1

公开(公告)日：2025-03-06

申请号：US18788588

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Akshay N. Singh ,  Kunal R. Parekh ,  Bharat Bhushan

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor device assembly with layered dielectric is disclosed. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die coupled with the first semiconductor die. The second semiconductor die is at least partially surrounded by a tensile dielectric and a compressive dielectric disposed at the first semiconductor die. The tensile dielectric is configured to experience tensile stress at an upper surface and compressive stress at a lower surface (e.g., the tensile dielectric will warp concave down). In contrast, the compressive dielectric is configured to experience compressive stress at an upper surface and tensile stress at a lower surface (e.g., the compressive dielectric will warp concave up). As a result, stress in the semiconductor device assembly can be reduced and overall yield can be improved.

公开(公告)号：US20240079369A1

公开(公告)日：2024-03-07

申请号：US17938917

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Bret K. Street ,  Wei Zhou ,  Kyle K. Kirby ,  Amy R. Griffin ,  Thiagarajan Raman ,  Jaekyu Song

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/48 ,  H01L24/16 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48011 ,  H01L2224/4809 ,  H01L2224/48145 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: This document discloses techniques, apparatuses, and systems for connecting semiconductor dies through traces. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first dielectric layer at which first circuitry is disposed. The second semiconductor die includes a second dielectric layer at which second circuitry is disposed. One or more traces extend from a side surface of the first dielectric layer and at a side surface of the second dielectric layer to electrically couple the first circuitry and the second circuitry. In doing so, rigid connective structures may not be needed to couple the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240063207A1

公开(公告)日：2024-02-22

申请号：US17892038

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Terrence B. McDaniel ,  Amy R. Griffin ,  Kyle K. Kirby ,  Thiagarajan Raman

IPC: H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/34 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L21/568 ,  H01L24/11 ,  H01L24/80 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L23/345 ,  H01L23/3135 ,  H01L2221/68381 ,  H01L2221/68368 ,  H01L2224/0557 ,  H01L2224/06134 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2224/80006

Abstract: Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

公开(公告)号：US20240055400A1

公开(公告)日：2024-02-15

申请号：US17884475

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Bret K. Street ,  Kyle K. Kirby ,  Wei Zhou ,  Thiagarajan Raman

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582

Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.

公开(公告)号：US20230238300A1

公开(公告)日：2023-07-27

申请号：US17583038

申请日：2022-01-24

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Kyle K. Kirby

IPC: H01L23/373 ,  H01L23/31 ,  H01L23/544 ,  H01L21/56 ,  H01L25/16 ,  H01L21/603

CPC classification number: H01L23/3736 ,  H01L23/3107 ,  H01L23/544 ,  H01L21/568 ,  H01L21/561 ,  H01L25/16 ,  H01L21/603

Abstract: A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

公开(公告)号：US11658129B2

公开(公告)日：2023-05-23

申请号：US16950379

申请日：2020-11-17

Applicant: Micron Technology, Inc.

Inventor： Bret K. Street

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/373 ,  H01L21/326 ,  H01L21/324 ,  F03G7/06

CPC classification number: H01L23/562 ,  H01L21/326 ,  H01L21/3247 ,  H01L23/373 ,  F03G7/065

Abstract: A semiconductor device assembly including a shape-memory element connected to at least one component of the semiconductor device assembly. The shape-memory element may be temperature activated or electrically activated. The shape-memory element is configured to move to reduce, minimize, or modify a warpage of a component of the assembly by moving to an initial shape. The shape-memory element may be applied to a surface of a component of the semiconductor device assembly or may be positioned within a component of the semiconductor device assembly such as a layer. The shape-memory element may be connected between two components of the semiconductor device assembly. A plurality of shape-memory elements may be used to reduce, minimize, and/or modify warpage of one or more components of a semiconductor device assembly.

公开(公告)号：US20220375902A1

公开(公告)日：2022-11-24

申请号：US17817690

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L21/78 ,  H01L21/66 ,  H01L25/00 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US20210183716A1

公开(公告)日：2021-06-17

申请号：US17170120

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Mark E. Tuttle

IPC: H01L23/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L25/00

Abstract: A semiconductor device includes a substrate; a die attached over the substrate; and a metal enclosure continuously encircling a space and extending vertically between the substrate and the die.

公开(公告)号：US10943842B2

公开(公告)日：2021-03-09

申请号：US16775163

申请日：2020-01-28

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L23/10 ,  H01L25/065 ,  H01L23/04 ,  H01L25/00

Abstract: A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.