公开(公告)号：US20180137416A1

公开(公告)日：2018-05-17

申请号：US15871660

申请日：2018-01-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06N3/08 ,  G06N3/063 ,  G06K9/00

CPC classification number: G06N3/08 ,  G06K9/00986 ,  G06N3/063

Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

公开(公告)号：US20180089113A1

公开(公告)日：2018-03-29

申请号：US15280611

申请日：2016-09-29

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F13/12 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/126 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/404 ,  G06F2213/2802

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US20180075165A1

公开(公告)日：2018-03-15

申请号：US15806073

申请日：2017-11-07

Applicant: Micron Technology Inc.

Inventor： Harold B. Noyes ,  David R. Brown

IPC: G06F17/30 ,  G06F11/30

Abstract: Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor may control the saving of state variables from the state variable array to the state variable storage array. The state variable storage control logic may also control restoring of the state variables from the state variable storage array to restore a search state.

公开(公告)号：US20170193351A1

公开(公告)日：2017-07-06

申请号：US14984955

申请日：2015-12-30

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Paul D. Dlugosch

IPC: G06N3/04 ,  G06K9/00 ,  G06K9/62

CPC classification number: G06K9/00973 ,  G06N5/02

Abstract: An apparatus includes a state machine lattice. The apparatus also includes a memory. The memory of the apparatus is configured to receive an event vector, such that the event vector includes an indication of a result of data analysis using the state machine lattice. The apparatus further includes a control system. The control system of the apparatus is configured to selectively provide only a portion of the event vector.

公开(公告)号：US09509312B2

公开(公告)日：2016-11-29

申请号：US14832543

申请日：2015-08-21

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Irene Junjuan Xu

IPC: H03K19/177 ,  H03K19/20 ,  G05B19/045 ,  G06F9/44 ,  G06F17/50 ,  H03K19/0175 ,  G06F7/00

CPC classification number: H03K19/17708 ,  G05B19/045 ,  G06F7/00 ,  G06F9/4498 ,  G06F17/5054 ,  H03K19/0175 ,  H03K19/17704 ,  H03K19/20 ,  H03K19/21 ,  Y02T10/82

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may includes a programmable Boolean logic cell that may be programmed to perform various logic functions on a data stream. The programmability includes an inversion of a first input to the Boolean logic cell, an inversion of a last output of the Boolean logic cell, and a selection of an AND gate or an OR gate as a final output of the Boolean logic cell. The Boolean logic cell also includes end of data circuitry configured to cause the Boolean logic cell to only output after an end of data signifying the end of a data stream is received at the Boolean logic cell.

公开(公告)号：US09448965B2

公开(公告)日：2016-09-20

申请号：US14065168

申请日：2013-10-28

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit S. Bains

IPC: G06F15/78 ,  G06F9/44

CPC classification number: G06F13/4027 ,  G06F9/4498 ,  G06F15/7867 ,  G06N3/08

Abstract: An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.

Abstract translation: 装置可以包括被配置为从处理器接收数据流的第一部分的第一状态机引擎和被配置为从处理器接收数据流的第二部分的第二状态机引擎。 该装置包括缓冲器接口，该缓冲器接口被配置为使能第一和第二状态机引擎之间的数据传输。 缓冲器接口包括耦合到第一和第二状态机引擎的接口数据总线。 缓冲器接口被配置为在第一和第二状态机引擎之间提供数据。

公开(公告)号：US20160239440A1

公开(公告)日：2016-08-18

申请号：US15045550

申请日：2016-02-17

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Irene Junjuan Xu ,  Paul Glendenning

IPC: G06F13/16 ,  G06F13/12 ,  G06F13/40 ,  H04L12/883 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F9/4498 ,  G06F13/124 ,  G06F13/4022 ,  G06F13/4282 ,  G06F17/30516 ,  G06K9/00496 ,  G06K9/00973 ,  G06K9/00979 ,  H04L49/9021

Abstract: A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a data stream. The routing buffer also includes a second port configured to selectively provide the signal to a first routing line of a block of a state machine at a first time. The routing buffer further includes a third port configured to selectively provide the signal to a second routing line of the block of the state machine at the first time.

公开(公告)号：US20150324129A1

公开(公告)日：2015-11-12

申请号：US14756000

申请日：2015-06-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G05B19/045 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G06F7/00 ,  G06F9/4498

Abstract: A state machine engine includes a storage element, such as a (e.g., match) results memory. The storage element is configured to receive a result of an analysis of data. The storage element is also configured to store the result in a particular portion of the storage element based on a characteristic of the result. The storage element is additionally configured to store a result indicator corresponding to the result. Other state machine engines and methods are also disclosed.

Abstract translation: 状态机引擎包括诸如（例如，匹配）结果存储器的存储元件。 存储元件被配置为接收数据分析的结果。 存储元件还被配置为基于结果的特性将结果存储在存储元件的特定部分中。 存储元件还被配置为存储对应于结果的结果指示符。 还公开了其他状态机引擎和方法。

公开(公告)号：US08589641B2

公开(公告)日：2013-11-19

申请号：US13677771

申请日：2012-11-15

Applicant: Micron Technology, Inc.

Inventor： Brian Huber ,  Frank Ross ,  David R. Brown

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C7/1045 ,  G11C7/1051 ,  G11C11/4078

Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.

Abstract translation: 公开了诸如那些涉及固态存储器件的方法和装置，该固态存储器件包括配置成以组合的并行和串行读取方案读取的状态寄存器。 一种这样的固态存储器包括状态寄存器，其被配置为存储指示存储器的状态信息的多个位。 在存储器件中提供状态信息的一种这样的方法包括以并行形式提供存储器件的状态信息。 该方法还包括响应于接收至少一个读取命令以并行形式提供状态信息之后以串行形式提供状态信息。

公开(公告)号：US20230393929A1

公开(公告)日：2023-12-07

申请号：US17829576

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Parthasarathy Gajapathy ,  David R. Brown

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673

Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.