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公开(公告)号：US07402875B2
公开(公告)日：2008-07-22
申请号：US11207051
申请日：2005-08-17
申请人： Suman Datta , Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Gilbert Dewey , Mark L. Doczy , Robert S. Chau
发明人： Suman Datta , Justin K. Brask , Jack Kavalieros , Brian S. Doyle , Gilbert Dewey , Mark L. Doczy , Robert S. Chau
IPC分类号： H01L29/72
CPC分类号： H01L29/42376 , H01L21/28114 , H01L29/42384 , H01L29/495 , H01L29/517 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.
摘要翻译： 本发明的实施例提供一种具有金属栅极，高k栅极电介质层，金属栅极下方距离的源极/漏极延伸部以及金属栅极侧面中的横向底切的器件。
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公开(公告)号：US07235809B2
公开(公告)日：2007-06-26
申请号：US11292911
申请日：2005-12-01
申请人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L29/06
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681
摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。
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公开(公告)号：US07138316B2
公开(公告)日：2006-11-21
申请号：US10669064
申请日：2003-09-23
申请人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681
摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。
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64.发明申请公开(公告)号：US20090302350A1
公开(公告)日：2009-12-10
申请号：US12541763
申请日：2009-08-14
IPC分类号： H01L29/78
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/517 , H01L29/66628 , H01L29/7848 , Y10S438/933 , Y10S438/938
摘要： Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
摘要翻译： 描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。 源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。
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65.发明授权公开(公告)号：US07592213B2
公开(公告)日：2009-09-22
申请号：US11323688
申请日：2005-12-29
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/517 , H01L29/66628 , H01L29/7848 , Y10S438/933 , Y10S438/938
摘要： Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
摘要翻译： 描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。 源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。
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公开(公告)号：US20100248209A1
公开(公告)日：2010-09-30
申请号：US11478335
申请日：2006-06-30
IPC分类号： G01R27/28 , H01L29/78 , H01L29/66 , H01L21/28 , G01N27/00 , C12Q1/70 , C12Q1/02 , G01N33/92 , G01N33/00 , G01N33/53 , G01N33/68
CPC分类号： G01N27/4145 , G01N27/4146 , Y10T436/143333
摘要： The embodiments of the invention relate to a device having a first substrate comprising a transistor; a second substrate; an insulating layer in between and adjoining the first and second substrates; and an opening within the second substrate, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening. Other embodiments relate to a method including providing a substrate comprising a first part, a second part, and an insulating layer in between and adjoining the first and second parts; fabricating a transistor on the first part; and fabricating an opening within the second part, the opening being aligned with the transistor; wherein the transistor is configured to detect an electrical charge change within the opening.
摘要翻译： 本发明的实施例涉及具有包括晶体管的第一衬底的器件; 第二基板; 位于第一和第二基板之间并邻接第一和第二基板的绝缘层; 以及在所述第二基板内的开口，所述开口与所述晶体管对准; 其中所述晶体管被配置为检测所述开口内的电荷变化。 其他实施例涉及一种方法，包括提供在第一和第二部分之间并与之相邻的第一部分，第二部分和绝缘层的基底; 在第一部分制造晶体管; 以及在所述第二部分内制造开口，所述开口与所述晶体管对准; 其中所述晶体管被配置为检测所述开口内的电荷变化。
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67.发明授权公开(公告)号：US08120065B2
公开(公告)日：2012-02-21
申请号：US12541763
申请日：2009-08-14
IPC分类号： H01L21/02
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/517 , H01L29/66628 , H01L29/7848 , Y10S438/933 , Y10S438/938
摘要： Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
摘要翻译： 描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。 源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。
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68.发明申请Mechanism for forming a remote delta doping layer of a quantum well structure 有权用于形成量子阱结构的远程δ掺杂层的机理公开(公告)号：US20080237573A1
公开(公告)日：2008-10-02
申请号：US11731266
申请日：2007-03-29
IPC分类号： H01L29/06
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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69.发明授权Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric 失效用于在其栅极电介质中具有碳纳米管通道和电浮置量子点的非易失性存储器件的晶体管公开(公告)号：US07608883B2
公开(公告)日：2009-10-27
申请号：US12072971
申请日：2008-02-28
申请人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Justin Brask , Brian Doyle , Robert Chau
发明人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Justin Brask , Brian Doyle , Robert Chau
IPC分类号： H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L29/78696 , H01L51/0048 , H01L51/0541
摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.
摘要翻译： 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。
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70.发明申请Narrow-body multiple-gate FET with dominant body transistor for high performance 审中-公开具有主体晶体管的窄体多栅极FET，用于高性能公开(公告)号：US20070090408A1
公开(公告)日：2007-04-26
申请号：US11240487
申请日：2005-09-29
申请人： Amlan Majumdar , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Matthew Metz , Marko Radosavljevic , Been-Yih Jin , Robert Chau
发明人： Amlan Majumdar , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Matthew Metz , Marko Radosavljevic , Been-Yih Jin , Robert Chau
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/785 , H01L29/7854
摘要： A field-effect transistor for a narrow-body, multiple-gate transistor such as a FinFET, tri-gate or Ω-FET is described. The corners of the channel region disposed beneath the gate are rounded n, for instance, oxidation steps, to reduce the comer effect associated with conduction initiating in the corners of the channel region.
摘要翻译： 描述了用于诸如FinFET，三栅极或者Omega-FET的窄体多栅极晶体管的场效应晶体管。 设置在栅极下方的通道区域的角部是圆形的，例如氧化步骤，以减少与沟道区域的拐角中的传导起始相关的拐角效应。
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