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公开(公告)号：US20180351094A1
公开(公告)日：2018-12-06
申请号：US15994815
申请日：2018-05-31
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Andrea Redaelli
CPC classification number: H01L45/1293 , H01L27/2427 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1608
Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.
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公开(公告)号：US20180315797A1
公开(公告)日：2018-11-01
申请号：US15497503
申请日：2017-04-26
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Agostino Pirovano , Andrea Redaelli
IPC: H01L27/24 , H01L27/11514
CPC classification number: H01L27/2481 , H01L27/2409 , H01L27/2427 , H01L45/1675
Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.
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公开(公告)号：US20180315475A1
公开(公告)日：2018-11-01
申请号：US15582329
申请日：2017-04-28
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli , Fabio Pellizzer
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0073 , G11C2213/52 , H01L27/2463 , H01L45/08 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
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公开(公告)号：US09947719B2
公开(公告)日：2018-04-17
申请号：US15297925
申请日：2016-10-19
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano
CPC classification number: H01L27/2409 , G11C13/00 , G11C13/0004 , G11C13/0014 , G11C13/0016 , G11C2213/72 , H01L27/2481 , H01L27/285 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/14 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/1608
Abstract: Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.
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公开(公告)号：US09871078B2
公开(公告)日：2018-01-16
申请号：US15421855
申请日：2017-02-01
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Andrea Redaelli
CPC classification number: H01L27/2481 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is vertically offset relative to the first memory cell. Some embodiments include a memory array having a series of data/sense lines extending along a first direction, a series of access lines extending along a second direction, and memory cells vertically between the access lines and data/sense lines. The memory cells are arranged in a grid having columns along the first direction and rows along the second direction. Memory cells in a common column and/or row as one another are arranged in two alternating sets, with a first set having memory cells at a first height and a second set having memory cells at a second height vertically offset relative to the first height. Some embodiments include methods of forming memory arrays.
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Patent Agency Ranking
公开(公告)号：US20170365353A1
公开(公告)日：2017-12-21
申请号：US15691465
申请日：2017-08-30
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli
CPC classification number: G11C17/18 , G11C13/0004 , G11C13/0069 , G11C14/009 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/52 , G11C2213/72
Abstract: Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
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公开(公告)号：US20170263685A1
公开(公告)日：2017-09-14
申请号：US15607786
申请日：2017-05-30
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli
CPC classification number: H01L27/2481 , G11C13/0004 , G11C13/0023 , G11C13/003 , G11C2213/71 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
Abstract: Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.
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68.发明授权公开(公告)号：US09755145B2
公开(公告)日：2017-09-05
申请号：US15279158
申请日：2016-09-28
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Giorgio Servalli , Carmela Cupeta , Fabio Pellizzer
CPC classification number: H01L45/1293 , H01L27/2463 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/144 , H01L45/1608 , H01L45/1666 , H01L45/1675
Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.
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公开(公告)号：US09748480B2
公开(公告)日：2017-08-29
申请号：US15287609
申请日：2016-10-06
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Cinzia Perrone
IPC: H01L29/792 , H01L45/00 , H01L23/525 , H01L27/24 , H01L23/48
CPC classification number: H01L45/141 , H01L23/481 , H01L23/5256 , H01L27/2463 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/122 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L2924/0002 , H01L2924/00
Abstract: Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.
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70.发明授权公开(公告)号：US09640254B2
公开(公告)日：2017-05-02
申请号：US14551317
申请日：2014-11-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Andrea Redaelli
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0028 , G11C13/0033 , G11C13/004 , G11C2013/008 , G11C2013/0088 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/144
Abstract: Memories and methods of operating memories having memory cells sharing a resistance variable material.
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