公开(公告)号：US11152388B2

公开(公告)日：2021-10-19

申请号：US16653062

申请日：2019-10-15

Applicant: Micron Technology, Inc.

Inventor： Cole Smith ,  Ramey M. Abdelrahaman ,  Silvia Borsari ,  Chris M. Carlson ,  David Daycock ,  Matthew J. King ,  Jin Lu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

公开(公告)号：US20200035795A1

公开(公告)日：2020-01-30

申请号：US16589985

申请日：2019-10-01

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L21/28

Abstract: Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.

公开(公告)号：US10460943B2

公开(公告)日：2019-10-29

申请号：US15149553

申请日：2016-05-09

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L21/28

Abstract: Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.

公开(公告)号：US20190267397A1

公开(公告)日：2019-08-29

申请号：US16410992

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792

Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

公开(公告)号：US10388665B1

公开(公告)日：2019-08-20

申请号：US15992959

申请日：2018-05-30

Applicant: Micron Technology, Inc.

Inventor： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

公开(公告)号：US20190109190A1

公开(公告)日：2019-04-11

申请号：US16197217

申请日：2018-11-20

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson

IPC: H01L29/06 ,  H01L27/11582 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11556

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.

公开(公告)号：US20180358377A1

公开(公告)日：2018-12-13

申请号：US16102987

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/51 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/518 ,  H01L29/7926

Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

公开(公告)号：US20130316153A1

公开(公告)日：2013-11-28

申请号：US13956211

申请日：2013-07-31

Applicant: Micron Technology, Inc.

Inventor： Nik Mirin ,  Tsai-Yu Huang ,  Vishwanath Bhat ,  Chris M. Carlson ,  Vassil N. Antonov

IPC: C01G23/04 ,  H05K1/02 ,  H01L23/373

CPC classification number: H01L21/02186 ,  C01G23/04 ,  C23C16/405 ,  C23C16/45534 ,  H01G4/085 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02233 ,  H01L21/02244 ,  H01L21/28556 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H05K1/0203 ,  Y10T428/24802 ,  Y10T428/24975 ,  H01L2924/00

Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.

Abstract translation: 一些实施方案包括形成金红石型氧化钛的方法。 可以形成单层的氮化钛。 然后氮化钛单层可以在小于或等于约550℃的温度下被氧化，以将其转化为金红石型氧化钛的单层。 一些实施方案包括形成具有金红石型氧化钛电介质的电容器并且具有至少一个包含氮化钛的电极的方法。 一些实施方案包括含有氮化钛和金红石型氧化钛的导热叠层，并且一些实施方案包括形成这种叠层的方法。