公开(公告)号：US11984174B2

公开(公告)日：2024-05-14

申请号：US17249448

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Tawalin Opastrakoon ,  Renato C. Padilla ,  Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Michael G. Miller ,  Gary F. Besinga ,  Christopher M. Smitchger

IPC: G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3468 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: A configuration setting manager of a memory device receives a request to perform an adjustment operation on a set of configuration setting values for the memory device, where each configuration setting value of the set of configuration setting values is stored in a corresponding configuration register of a set of configuration registers; determines a configuration adjustment definition associated with one or more configuration setting values of the set of configuration setting values; calculates an updated set of configuration setting values by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and stores the updated set of configuration setting values in the corresponding configuration registers.

公开(公告)号：US11914876B2

公开(公告)日：2024-02-27

申请号：US17444416

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0685

Abstract: The occurrence of an asynchronous power loss (APL) event is detected in a memory sub-system. In response, an APL handling operation is performed. The APL handing operation includes identifying a last written page at a first page location in a block of the memory device, wherein the last written page is associated with a memory cell of the memory device, copying data from the last written page and from a related page associated with the memory cell to a temporary storage area in the memory device, copying the data from the temporary storage area to a second page location in the block of the memory device, and providing a notification that the memory device has recovered from the APL event.

公开(公告)号：US11720259B2

公开(公告)日：2023-08-08

申请号：US17747548

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Gary F. Besinga

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

公开(公告)号：US11586357B2

公开(公告)日：2023-02-21

申请号：US17332468

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C11/56

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

公开(公告)号：US20230049877A1

公开(公告)日：2023-02-16

申请号：US17978050

申请日：2022-10-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tawalin Opastrakoon ,  Renato C. Padilla ,  Michael G. Miller ,  Christopher M. Smitchger ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A first host data item and a second host data item are received. The first host data item is stored in a first page of a first logical unit of a memory device, where the first page is one of a plurality of pages associated with redundancy metadata. A second page a second page of a second logical unit of the memory device is identified, where the second page is one of the plurality of pages associated with the redundancy metadata, and the first page and the second page are associated with different wordlines of the memory device. The second host data item is stored in the second page of the second logical unit of the memory device. The first page and the second page can be associated with a fault tolerant stripe that includes the redundancy metadata.

公开(公告)号：US20220392561A1

公开(公告)日：2022-12-08

申请号：US17888641

申请日：2022-08-16

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C16/10 ,  G11C29/42 ,  G11C29/00 ,  G11C16/26 ,  G11C29/50

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.

公开(公告)号：US11416391B2

公开(公告)日：2022-08-16

申请号：US17149349

申请日：2021-01-14

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Daniel J. Hubbard ,  Renato C. Padilla ,  Ashutosh Malshe ,  Harish R. Singidi

IPC: G06F12/02 ,  G06F3/06

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

公开(公告)号：US20210286525A1

公开(公告)日：2021-09-16

申请号：US17332468

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C11/56

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.

公开(公告)号：US10854305B2

公开(公告)日：2020-12-01

申请号：US16820636

申请日：2020-03-16

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Walter Di Francesco ,  Renato C. Padilla ,  Gary F. Besinga ,  Violante Moschiano

IPC: G11C16/34 ,  G11C16/04 ,  G11C29/50 ,  G11C29/52 ,  G06F12/02

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator is readable. Responsive to determining that the status indicator readable, it can be determined that programming of data to the data block of the memory component did complete and there is a data retention loss.

公开(公告)号：US10593412B2

公开(公告)日：2020-03-17

申请号：US16040382

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Kishore Kumar Muchherla ,  Harish R. Singidi ,  Walter Di Francesco ,  Renato C. Padilla ,  Gary F. Besinga ,  Violante Moschiano

IPC: G11C16/34 ,  G11C29/50 ,  G11C16/04 ,  G11C29/52 ,  G06F12/02

Abstract: An indication of an initialization of power to a memory component can be received. In response to receiving the indication of the initialization, a last written page of a data block of the memory component can be identified. The last written page is associated with a status indicator. A determination is made of whether the status indicator can be read. Responsive to determining that the status indicator cannot be read, it can be determined that programming of data to the data block of the memory component did not complete based on a prior loss of power to the memory component.