公开(公告)号：US06706571B1

公开(公告)日：2004-03-16

申请号：US10274951

申请日：2002-10-22

Applicant: Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

Inventor： Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78684

Abstract: A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures.

Abstract translation: 在半导体器件中形成多个结构的方法包括在导电层上沉积膜，蚀刻膜的一部分中的沟槽并且形成在沟槽的侧壁附近。 然后可以对该膜进行蚀刻，然后进行导电层的形成以形成结构。

公开(公告)号：US06657267B1

公开(公告)日：2003-12-02

申请号：US10163930

申请日：2002-06-06

Applicant: Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Bin Yu

Inventor： Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/517 ,  H01L21/2652 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

Abstract: A semiconductor device and method of fabrication are disclosed. The semiconductor device includes a liner composed of a high-K material. The liner has a portion separating a sidewall spacer from a gate and a portion separating the sidewall spacer from a layer of semiconductor material. The liner functions as an etch stop during formation of the sidewall spacer. The liner is removable by an etch process that has substantially no reaction with an isolation region formed in the layer of semiconductor material.

Abstract translation: 公开了半导体器件和制造方法。 半导体器件包括由高K材料构成的衬垫。 衬套具有将侧壁间隔物与栅极分离的部分和将侧壁间隔物与半导体材料层分离的部分。 衬垫在形成侧壁间隔物期间用作蚀刻停止。 衬里可以通过蚀刻工艺去除，该蚀刻工艺基本上不与半导体材料层中形成的隔离区域发生反应。

公开(公告)号：US06611029B1

公开(公告)日：2003-08-26

申请号：US10290158

申请日：2002-11-08

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.

Abstract translation: 半导体器件可以包括基板和形成在该副墨滴上的绝缘层。 鳍可以形成在绝缘层上，并且可以包括多个侧表面和顶表面。 第一栅极可以形成在靠近鳍片的多个侧表面中的一个的绝缘层上。 第二栅极，并且可以形成在与第一栅极分离并且靠近鳍片的多个侧表面中的另一个的绝缘层上。

公开(公告)号：US06528858B1

公开(公告)日：2003-03-04

申请号：US10044892

申请日：2002-01-11

Applicant: Bin Yu ,  Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Zoran Krivokapic

Inventor： Bin Yu ,  Qi Xiang ,  Olov Karlsson ,  HaiHong Wang ,  Zoran Krivokapic

IPC: H01L2902

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/76264 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor wafer including an NMOS device and a PMOS device. The NMOS device is formed to have a high-K gate dielectric and the PMOS device is formed to have a standard-K gate dielectric. A method of forming the NMOS device and the PMOS device is also disclosed.

Abstract translation: 一种包括NMOS器件和PMOS器件的半导体晶片。 NMOS器件形成为具有高K栅极电介质，并且PMOS器件形成为具有标准K栅极电介质。 还公开了形成NMOS器件和PMOS器件的方法。

公开(公告)号：US06448165B1

公开(公告)日：2002-09-10

申请号：US09746397

申请日：2000-12-21

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L213205

CPC classification number: H01L21/28123 ,  H01L21/32134 ,  Y10S977/707 ,  Y10S977/888 ,  Y10S977/891 ,  Y10S977/892

Abstract: For fabricating a field effect transistor within an active device area of a semiconductor substrate, a layer of gate dielectric material is deposited on the semiconductor substrate. A layer of gate electrode material is deposited on the layer of gate dielectric material, and the gate electrode material is a semiconductor material. At least one of an N-type dopant or a P-type dopant or a neutral dopant is implanted into the layer of gate electrode material such that the at least one of an N-type dopant or a P-type dopant or a neutral dopant has a dopant concentration in the layer of gate electrode material. A layer of photo-resist material, a layer of BARC (bottom anti-reflective coating) material, and the layer of gate electrode material are patterned to form a gate structure of the field effect transistor. The gate structure is comprised of the remaining gate electrode material, and the BARC (bottom anti-reflective coating) material remains on the gate structure. The BARC (bottom anti-reflective coating) material is then stripped from the gate structure using an etching reactant that etches both of the BARC (bottom anti-reflective coating) material and the gate electrode material. An etch rate of the gate electrode material in the etching reactant increases with an increase of the dopant concentration of the at least one of an N-type dopant or a P-type dopant or a neutral dopant within the gate electrode material. Sidewalls of the gate structure are trimmed by a trim length during the step of stripping the BARC (bottom anti-reflective coating) material from the gate structure. Thus, the dopant concentration of the at least one of an N-type dopant or a P-type dopant or a neutral dopant in the gate electrode material is adjusted to control the trim length of the gate structure.

Abstract translation: 为了在半导体衬底的有源器件区域内制造场效应晶体管，在半导体衬底上沉积一层栅介质材料。 栅极材料层沉积在栅极介电材料层上，栅电极材料是半导体材料。 N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种注入到栅电极材料层中，使得N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种 在栅极材料层中具有掺杂剂浓度。 将一层光致抗蚀剂材料，一层BARC（底部抗反射涂层）材料和该栅极电极材料层图案化以形成该场效应晶体管的栅极结构。 栅极结构由剩余的栅电极材料组成，并且BARC（底部抗反射涂层）材料保留在栅极结构上。 然后使用蚀刻BARC（底部抗反射涂层）材料和栅电极材料的蚀刻反应物，从栅极结构剥离BARC（底部抗反射涂层）材料。 蚀刻反应物中的栅电极材料的蚀刻速率随着栅极电极材料中的N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种的掺杂剂浓度的增加而增加。 在从栅极结构剥离BARC（底部抗反射涂层）材料的步骤期间，栅极结构的侧壁被修剪长度。 因此，调整栅电极材料中的N型掺杂剂或P型掺杂剂或中性掺杂剂中的至少一种的掺杂剂浓度以控制栅极结构的修整长度。

公开(公告)号：US07262104B1

公开(公告)日：2007-08-28

申请号：US10857931

申请日：2004-06-02

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Bin Yu

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semiconductor devices.

Abstract translation: 形成具有不同阈值电压的多个半导体器件。 根据一个示例性实施例，第一和第二半导体器件被形成和掺杂不同，导致第一和第二半导体器件的不同阈值电压。

公开(公告)号：US07259425B2

公开(公告)日：2007-08-21

申请号：US10348911

申请日：2003-01-23

Applicant: Judy Xilin An ,  Haihong Wang ,  Bin Yu

Inventor： Judy Xilin An ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

Abstract: A triple gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin structure, a first gate formed adjacent a first side of the fin structure, a second gate formed adjacent a second side of the fin structure opposite the first side, and a top gate formed on top of the fin structure. A gate around MOSFET includes multiple fins, a first sidewall gate structure formed adjacent one of the fins, a second sidewall gate structure formed adjacent another one of the fins, a top gate structure formed on one or more of the fins, and a bottom gate structure formed under one or more of the fins.

Abstract translation: 三栅极金属氧化物半导体场效应晶体管（MOSFET）包括翅片结构，邻近翅片结构的第一侧形成的第一栅极，与第一侧相对的翅片结构的第二侧附近形成的第二栅极，以及 形成在鳍结构顶部的顶门。 MOSFET周围的栅极包括多个散热片，邻近其中一个翅片形成的第一侧壁栅极结构，邻近另一个鳍片形成的第二侧壁栅极结构，形成在一个或多个翅片上的顶部栅极结构，以及底部栅极 在一个或多个翅片下形成的结构。

公开(公告)号：US07256455B2

公开(公告)日：2007-08-14

申请号：US10720166

申请日：2003-11-25

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.

Abstract translation: 半导体器件可以包括衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电鳍。 导电翅片可以包括多个侧表面和顶表面。 半导体器件还可以包括形成在与导电鳍片的第一端相邻的绝缘层上的源极区域和形成在与导电鳍片的第二端相邻的绝缘层上的漏极区域。 半导体器件还可以包括在半导体器件的沟道区域中形成在与绝缘层相邻的导电鳍片上的金属栅极。

公开(公告)号：US07186599B2

公开(公告)日：2007-03-06

申请号：US10754540

申请日：2004-01-12

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.

Abstract translation: 形成鳍状场效应晶体管的方法包括：在鳍片的第一端上形成翅片并形成源极区域，在鳍片的第二端部形成漏极区域。 该方法还包括在鳍上形成具有第一图案的第一半导体材料的虚拟栅极，并在虚拟栅极周围形成介电层。 该方法还包括去除第一半导体材料以在对应于第一图案的电介质层中留下沟槽，使在沟槽内暴露的鳍片的一部分变薄，并在沟槽内形成金属栅极。

公开(公告)号：US07148526B1

公开(公告)日：2006-12-12

申请号：US10348758

申请日：2003-01-23

Applicant: Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Judy Xilin An ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/7855 ,  H01L21/823821 ,  H01L29/42384 ,  H01L29/7843 ,  H01L29/78684

Abstract: A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.

Abstract translation: 双栅极锗金属氧化物半导体场效应晶体管（MOSFET）包括锗翅片，邻近锗翅片的第一侧形成的第一栅极和与第一侧相对的锗翅片第二侧附近形成的第二栅极 。 三栅极MOSFET包括锗翅片，与锗翅片的第一侧相邻形成的第一栅极，与第一侧相对的锗翅片的第二侧附近形成的第二栅极和形成在锗翅片顶部上的顶栅极 。 全栅极MOSFET包括锗翅片，邻近锗翅片的第一侧形成的第一侧壁栅极结构，邻近锗翅片的第二侧形成的第二侧壁栅极结构，以及形成在锗翅片上和周围的附近的栅极结构 锗鳍