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公开(公告)号：US07126986B2
公开(公告)日：2006-10-24
申请号：US10262359
申请日：2002-09-30
CPC分类号： G06F1/12 , H03L7/0814 , H03L7/089 , H03L7/093 , H04L7/0008 , H04L7/0025
摘要： A method and system for improved phase tracking in communication systems is disclosed. In one embodiment, a method, comprises identifying a slow-time varying phase drift on a link by counting long term beats; calibrating an interpolator with the phase drift; predicting a future phase drift; and updating the interpolator periodically with the future phase drift prediction.
摘要翻译： 公开了一种用于改进通信系统中的相位跟踪的方法和系统。 在一个实施例中，一种方法包括通过计数长期节拍来识别链路上的慢时变化相位漂移; 校准具有相位漂移的内插器; 预测未来相位漂移; 以及随着未来的相位漂移预测周期性地更新内插器。
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公开(公告)号：US07012304B1
公开(公告)日：2006-03-14
申请号：US09651385
申请日：2000-08-29
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： H01L23/62
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.
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公开(公告)号：US06922071B2
公开(公告)日：2005-07-26
申请号：US10330598
申请日：2002-12-27
申请人： Sanjay Dabral , Santanu Chaudhuri
发明人： Sanjay Dabral , Santanu Chaudhuri
IPC分类号： H03K19/173 , H03K17/16
CPC分类号： H03K19/1732
摘要： A method for setting multiple chip parameters using one IC terminal is described. The chip comprises a first circuit coupled to the pin for setting a first parameter. A second circuit coupled to the pin sets a second parameter. In addition, a third circuit coupled to the pin sets a third parameter of the chip.
摘要翻译： 描述使用一个IC终端设置多个芯片参数的方法。 芯片包括耦合到引脚的第一电路以设置第一参数。 耦合到引脚的第二电路设置第二参数。 此外，耦合到引脚的第三电路设置芯片的第三参数。
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公开(公告)号：US06561410B2
公开(公告)日：2003-05-13
申请号：US10116503
申请日：2002-04-03
申请人： Sanjay Dabral , Ming Zeng
发明人： Sanjay Dabral , Ming Zeng
IPC分类号： B23K3102
CPC分类号： H05K1/0246 , G06F13/4086 , H05K1/0298 , H05K1/181 , H05K2201/09236 , H05K2201/10545 , H05K2201/10689 , H05K2201/10734 , Y02P70/611 , Y10T29/49144 , Y10T29/49155
摘要： A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units having twin processors and a bridge chip set, yielding a motherboard having significantly lower number of metal layers, a faster bus and significantly improved noise margin, all with high density IC packages on a wide parallel bus.
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公开(公告)号：US06373715B1
公开(公告)日：2002-04-16
申请号：US09467300
申请日：1999-12-17
申请人： Ming Zeng , Sanjay Dabral
发明人： Ming Zeng , Sanjay Dabral
IPC分类号： H05K702
CPC分类号： H05K1/181 , H05K1/0298 , H05K7/1459 , H05K2201/09236 , H05K2201/10545 , H05K2201/10689 , H05K2201/10734 , Y02P70/611
摘要： A topology for mounting processors on opposite sides of a printed circuit board (PCB) orients rows of processor connection pins parallel to the bus orientation within the PCB and defines a relative 180 degree orientation between the opposing processors.
摘要翻译： 用于将处理器安装在印刷电路板（PCB）的相对侧上的拓扑结构将排列的处理器连接引脚平行于PCB内的总线方向定位，并定义相对的处理器之间的相对180度取向。
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66.发明授权
公开(公告)号：US6090650A
公开(公告)日：2000-07-18
申请号：US940303
申请日：1997-09-30
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： G06F13/40 , H01L21/8234 , H01L21/8238 , H01L29/423 , H03L7/00 , H01L21/337
CPC分类号： H03L7/00 , G06F13/4072 , H01L21/823418 , H01L21/823437 , H01L21/823828 , H01L29/4238 , H01L2924/0002
摘要： A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.
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公开(公告)号：US07610522B2
公开(公告)日：2009-10-27
申请号：US11322060
申请日：2005-12-28
IPC分类号： G01R31/28
CPC分类号： G06F11/221
摘要： A condition is detected to cause a component having physical layer circuitry with a transmitter and a receiver to enter a testing state. The transmitter transmits a pre-selected data pattern while comparing data received by the receiver to the pre-selected data pattern during a first phase of the testing state. The transmitter transmits data received by the receiver without comparing the data received by the receiver to the pre-selected data pattern during a second phase of the testing state.
摘要翻译： 检测到条件使得具有发射器和接收器的物理层电路的部件进入测试状态。 在测试状态的第一阶段期间，发射机发送预选数据模式，同时将接收机接收的数据与预先选择的数据模式进行比较。 在测试状态的第二阶段期间，发射机发送由接收机接收的数据而不将接收机接收的数据与预先选择的数据模式进行比较。
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68.发明授权公开(公告)号：US07525723B2
公开(公告)日：2009-04-28
申请号：US11479889
申请日：2006-06-30
申请人： Sanjay Dabral , Mohiuddin Mazumder , Hai-Feng Liu , Larry Tate
发明人： Sanjay Dabral , Mohiuddin Mazumder , Hai-Feng Liu , Larry Tate
CPC分类号： G02B6/43 , G01R1/071 , G02B2006/12138 , G02B2006/12159 , H01R13/6587
摘要： An electrical connector to be electrically disposed between a first circuit board and a second circuit board to electrically couple the first circuit board with the second circuit board is disclosed. The electrical connector may have an electro-optic modulator to modulate optical signals based on electrical signals exchanged between the first and second circuit boards through the electrical connector. Systems incorporating such electrical connectors, and methods of using the electrical connectors and systems, such as for debug, are also disclosed.
摘要翻译： 公开了一种电气设置在第一电路板和第二电路板之间以将第一电路板与第二电路板电耦合的电连接器。 电连接器可以具有电光调制器，用于基于通过电连接器在第一和第二电路板之间交换的电信号来调制光信号。 还公开了包括这种电连接器的系统，以及使用电连接器和系统的方法，例如用于调试。
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公开(公告)号：US07478257B2
公开(公告)日：2009-01-13
申请号：US10403145
申请日：2003-03-31
IPC分类号： G06F1/00
CPC分类号： H04L7/0337
摘要： According to some embodiments an apparatus comprising a vote generator, a vote governor, and a local clock controller is provided. The vote generator generates votes based on a local clock signal and transitions in a stream of received data. The vote governor receives the generated votes and discards at least some of the votes. The local clock controller adjusts the local clock signal based on a generated vote that has not been discarded.
摘要翻译： 根据一些实施例，提供了一种包括投票发生器，投票管理器和本地时钟控制器的装置。 投票生成器基于本地时钟信号生成投票并在接收的数据流中进行转换。 投票总监收到所产生的投票，并至少丢弃一些投票。 本地时钟控制器根据未被丢弃的生成的投票来调整本地时钟信号。
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