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61.发明申请公开(公告)号：US20210400820A1
公开(公告)日：2021-12-23
申请号：US17465292
申请日：2021-09-02
Applicant: RAYTHEON COMPANY
Inventor： James E. Benedict , Gregory G. Beninati , Mikhail Pevzner , Thomas V. Sikina , Andrew R. Southworth
Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.
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公开(公告)号：US11171101B2
公开(公告)日：2021-11-09
申请号：US16836470
申请日：2020-03-31
Applicant: RAYTHEON COMPANY
Inventor： James E. Benedict , Paul A. Danello , Mikhail Pevzner , Thomas V. Sikina , Andrew R. Southworth
IPC: H01L23/00
Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.
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公开(公告)号：US11158955B2
公开(公告)日：2021-10-26
申请号：US16183116
申请日：2018-11-07
Applicant: RAYTHEON COMPANY
Inventor： Thomas V. Sikina , John P. Haven , James E. Benedict , Jonathan E. Nufio-Molina , Andrew R. Southworth
IPC: H01Q1/52 , H01Q21/00 , H01P1/04 , H01Q13/10 , H01Q13/18 , H05K1/02 , H05K3/40 , H01P5/02 , H01Q17/00 , H01Q1/42 , H01Q1/44 , B33Y10/00 , B33Y70/00 , B33Y80/00
Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.
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公开(公告)号：US20210249787A1
公开(公告)日：2021-08-12
申请号：US16786880
申请日：2020-02-10
Applicant: RAYTHEON COMPANY
Inventor： Jack J. Schuss , Phillip W. Thiessen , Thomas V. Sikina
Abstract: A dual band dipole radiator array includes a high band radiator array disposed on a dielectric layer for transmitting and receiving high band radar signals; a low band radiator array disposed on a front side of the high band radiator array for transmitting and receiving low band radar signals; a foam material between the low band radiator array and the high band radiator array for support; and a single aperture for both the low band radiator array and the high band radiator array for transmitting and receiving the radar signals, where the low band radiator array is comprised of a plurality of dipole structures disposed within the foam material and tuned to pass through high band radar signals to or from the high band radiator array.
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公开(公告)号：US20210151855A1
公开(公告)日：2021-05-20
申请号：US16683593
申请日：2019-11-14
Applicant: RAYTHEON COMPANY
Inventor： Thomas V. Sikina , John P. Haven , Kevin Wilder , James E. Benedict , Andrew R. Southworth , Mary K. Herndon
Abstract: A communications array includes a support structure configured to array elements, and a plurality of array elements supported by the support structure. Each array element is fabricated from an advanced manufacturing techniques (AMT) process. The support structure may be fabricated from a printed circuit board (PCB) or similar dielectric material. Each array element may include a radiator and/or a beamformer manufactured using the AMT process. The communications array further may include a copper vertical launch (CVL) and/or an electromagnetic boundary.
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Patent Agency Ranking
公开(公告)号：US20200028257A1
公开(公告)日：2020-01-23
申请号：US16418231
申请日：2019-05-21
Applicant: RAYTHEON COMPANY
Inventor： James E. Benedict , John P. Haven , Peter J. Adams , Thomas V. Sikina
Abstract: A wave phased array is manufactured using additive manufacturing technology (AMT). The wave phased array includes a radiator, a radiator dilation layer supporting the radiator, a beamformer supporting the radiator dilation layer, a beamformer dilation layer supporting the beamformer, and a substrate support layer supporting the beamformer dilation layer. At least one of the radiator, the radiator dilation layer, the beamformer, the beamformer dilation layer and the substrate support layer is fabricated at least in part by an AMT process.
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公开(公告)号：US20190357363A1
公开(公告)日：2019-11-21
申请号：US16414112
申请日：2019-05-16
Applicant: RAYTHEON COMPANY
Inventor： Thomas V. Sikina , John P. Haven , Peter J. Adams , James E. Benedict , Carolyn R. Reistad
Abstract: A reactive beamformer includes a radiator disposed within a substrate and configured to radiate a received electromagnetic signal, a plurality of receptors disposed within the substrate, each of the plurality of receptors configured to receive a portion of the radiated electromagnetic signal, and a plurality of signal lines. Each signal line of the plurality of signal lines is coupled to a respective receptor of the plurality of receptors to convey the portion of the radiated electromagnetic signal from the respective receptor and to provide the portion of the radiated electromagnetic signal to an output.
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公开(公告)号：US20190150296A1
公开(公告)日：2019-05-16
申请号：US15988296
申请日：2018-05-24
Applicant: RAYTHEON COMPANY
Inventor： Andrew R. Southworth , Thomas V. Sikina , John P. Haven , James E. Benedict , Kevin Wilder
Abstract: Electromagnetic circuit structures and methods are provided for a circuit board that includes a hole disposed through a substrate to provide access to an electrical component, such as a signal trace line (or stripline), that is at least partially encapsulated (e.g., sandwiched) between substrates. The electrical component includes a portion substantially aligned with the hole, and an electrical conductor is disposed within the hole. The electrical conductor is soldered to the portion of the electrical component.
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公开(公告)号：US20190148807A1
公开(公告)日：2019-05-16
申请号：US16183169
申请日：2018-11-07
Applicant: RAYTHEON COMPANY
Inventor： Thomas V. Sikina , John P. Haven , James E. Benedict
CPC classification number: H01P3/08 , H01P3/085 , H01P11/003 , H05K1/0219 , H05K1/0224 , H05K1/115 , H05K3/0044 , H05K3/04 , H05K3/107 , H05K3/28 , H05K2201/093 , H05K2201/09854
Abstract: Circuits and methods include transmission lines formed from a conductive cladding on a substrate surface. The transmission line includes additional reference conductors positioned co-planar on the surface, including a gap between the transmission line and each of the reference conductors. The transmission line and the reference conductors are at least partially encapsulated (e.g., sandwiched) between two substrates. Isolation boundaries may be included as ground planes, e.g., above and below the transmission line, on opposing surfaces of the substrates, and Faraday walls, e.g., vertically, through the substrates. Current densities generated by various electromagnetic signals are distributed among the transmission line and the reference conductors (as a tri-conductor arrangement), and may be partially further distributed to the isolation (ground) boundaries.
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公开(公告)号：US20180183146A1
公开(公告)日：2018-06-28
申请号：US15390764
申请日：2016-12-27
Applicant: Raytheon Company
Inventor： Thomas V. Sikina , John P. Haven , Philip M. Henault , Alkim Akyurtlu
CPC classification number: H01Q3/34 , G01S13/02 , G01S2013/0254 , H01P5/16 , H01Q21/0075
Abstract: A via-less beamformer provided from a plurality of circuits elements having circuit layouts selected to mitigate unwanted reactive coupling there between. At least one of the plurality of circuit elements is provided having a circuit layout selected based upon reactive field theory. In one embodiment, a circuit layout may be selected by: determining which circuit features of the circuit elements produce reactive fields in response to a signal provided thereto, separating the total field into a modal set and determining the modal weighting coefficients based on geometrical and/or design features of the of the circuit elements. In one embodiment the via-less beamformer comprises one or more via-less combiner/divider circuits. In one embodiment the via-less beamformer comprises one or more branch hybrid coupler circuits. In one embodiment the via-less beamformer comprises one or more via-less combiner/divider circuits and one or more branch hybrid coupler circuits.
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