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公开(公告)号：US09467139B2
公开(公告)日：2016-10-11
申请号：US14641708
申请日：2015-03-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuya Onuki
IPC: G11C7/00 , H03K17/687 , H03K17/16
CPC classification number: H03K17/687 , H01L27/0207 , H01L29/78693 , H03K17/161 , H03K2217/0036
Abstract: A semiconductor device capable of reducing power consumption is provided. A writing potential is supplied to the cell 11 in which data rewriting is to be performed, whereby data is written. Meanwhile, in the cell 11 in which data rewriting is not to be performed, the data is transferred to the cell 12 and then the transferred data is rewritten to the cell 11. As a result, the data stored in the cell 11 in which data rewriting is not to be performed can be maintained without the reading and writing operation in a driver circuit. This results in a higher rewriting speed and lower power consumption in the driver circuit.
Abstract translation: 提供能够降低功耗的半导体器件。 将写入电势提供给要执行数据重写的单元11，从而写入数据。 同时，在不执行数据重写的单元11中，将数据传送到单元12，然后将所传送的数据重写到单元11.结果，存储在单元11中的数据，其中数据 在驱动电路中没有进行读写操作的情况下，不能进行重写。 这导致驱动电路中更高的重写速度和更低的功耗。
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公开(公告)号：US20140286073A1
公开(公告)日：2014-09-25
申请号：US14218058
申请日：2014-03-18
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Tatsuya Onuki
IPC: G11C7/12
CPC classification number: G11C11/565 , G11C11/403 , G11C11/4076 , G11C11/4091
Abstract: To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a low voltage is applied to a bit line and a first wiring to turn on the first Tr and the second Tr. In the second step, a first voltage is applied to the first wiring, and application of the low voltage to the bit line is stopped. Operation of reading the data is performed by a third step and a fourth step. In the third step, a high voltage is applied to the first wiring. In the fourth step, application of the high voltage to the first wiring is stopped, and a low voltage is applied to a capacitor line.
Abstract translation: 提供一种可写入和读出所需电位的半导体器件。 半导体器件包括第一晶体管（Tr），第二Tr和电容器。 在半导体装置中，通过第一步骤和第二步骤执行写入数据的操作。 在第一步骤中，将低电压施加到位线和第一布线以接通第一Tr和第二Tr。 在第二步骤中，向第一布线施加第一电压，停止向位线施加低电压。 通过第三步骤和第四步骤执行读取数据的操作。 在第三步骤中，向第一布线施加高电压。 在第四步骤中，停止向第一布线施加高电压，并且向电容器线施加低电压。
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公开(公告)号：US20130314976A1
公开(公告)日：2013-11-28
申请号：US13892479
申请日：2013-05-13
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuya Onuki
IPC: G11C11/40
CPC classification number: G11C11/40 , G11C14/0063 , H01L27/1108 , H01L27/1225
Abstract: To provide a memory element which keeps a stored logic state even without supply of power. To increase an effect of reducing power consumption by facilitating stop of supply of power to the memory element for a short time. Data (potential) held in a node in a logic circuit can be swiftly saved on a node where one of a source and a drain of the transistor and one electrode of the capacitor included in a memory circuit are connected by lowering a potential of the other electrode of a capacitor before a transistor is turned on. By making a potential of the other electrode of the capacitor when the transistor is in an off state higher than a potential of the other electrode of the capacitor when the transistor is in an on state, a potential of the node can be reliably held even without supply of power.
Abstract translation: 提供即使不提供电源也保持存储的逻辑状态的存储元件。 通过在短时间内有助于停止对存储元件供电的功率来增加降低功耗的效果。 保持在逻辑电路中的节点中的数据（电位）可以迅速地保存在晶体管的源极和漏极之一以及包含在存储器电路中的电容器的一个电极中的一个通过降低另一个的电位而连接的节点 在晶体管导通之前的电容器的电极。 当晶体管处于断开状态时，当晶体管处于导通状态时，通过使电容器的另一个电极的电位高于电容器的另一个电极的电位，即使没有 供电。
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64.发明授权公开(公告)号：US12219771B2
公开(公告)日：2025-02-04
申请号：US17621334
申请日：2020-06-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuya Onuki , Takanori Matsuzaki , Shunpei Yamazaki
Abstract: A semiconductor device having a large storage capacity is provided. The semiconductor device includes an oxide provided over a substrate, a plurality of first conductors over the oxide, a first insulator that is provided over the plurality of first conductors and includes a plurality of openings overlapping with regions between the plurality of first conductors, a plurality of second insulators provided in the respective plurality of openings, a plurality of charge retention layers provided over the respective plurality of second insulators, a plurality of third insulators provided over the respective plurality of charge retention layers, and a plurality of second conductors provided over the respective plurality of third insulators.
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公开(公告)号：US12199122B2
公开(公告)日：2025-01-14
申请号：US18105005
申请日：2023-02-02
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Tatsuya Onuki , Kiyoshi Kato , Takanori Matsuzaki , Hajime Kimura , Shunpei Yamazaki
IPC: H01L27/146 , H01L21/822 , H01L27/12 , H01L29/786 , H04N25/771 , H04N25/772 , H10B12/00
Abstract: An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.
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Patent Agency Ranking
公开(公告)号：US12193236B2
公开(公告)日：2025-01-07
申请号：US17772280
申请日：2020-11-13
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hitoshi Kunitake , Satoru Ohshita , Kazuki Tsuda , Tatsuya Onuki
Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.
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公开(公告)号：US12159573B2
公开(公告)日：2024-12-03
申请号：US18036931
申请日：2021-11-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Tatsuya Onuki , Hajime Kimura
IPC: G09G3/3208
Abstract: Provided is a display system with high display quality and high resolution. The display system includes a first layer and a display portion. The display portion is positioned in a region overlapping with the first layer. The first layer includes a semiconductor substrate containing silicon as a material, and a plurality of first transistors and a plurality of second transistors whose channel formation regions contain silicon are formed over the semiconductor substrate. The first layer includes a first circuit and a second circuit; the first circuit includes a driver circuit for driving the display portion; and the second circuit includes a memory device, a GPU, and an EL correction circuit. The display portion includes a pixel, and the pixel includes a light-emitting device containing organic EL and is electrically connected to the driver circuit. The memory device has a function of retaining image data; the GPU has a function of decoding the image data read from the memory device; and the EL correction circuit has a function of correcting light emitted from the light-emitting device.
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公开(公告)号：US12156410B2
公开(公告)日：2024-11-26
申请号：US17629804
申请日：2020-07-31
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Hajime Kimura , Takanori Matsuzaki , Tatsuya Onuki , Yuki Okamoto , Hideki Uochi , Satoru Okamoto , Hiromichi Godo , Kazuki Tsuda , Hitoshi Kunitake
Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.
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69.发明授权公开(公告)号：US12132057B2
公开(公告)日：2024-10-29
申请号：US17639744
申请日：2020-08-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hitoshi Kunitake , Tatsuya Onuki , Hajime Kimura , Takayuki Ikeda , Shunpei Yamazaki
IPC: H01L27/12 , H01L29/786 , H10B12/00
CPC classification number: H01L27/1255 , H01L27/1225 , H01L29/78648 , H01L29/7869 , H10B12/00
Abstract: A semiconductor device that occupies a small area is provided. The semiconductor device includes a first transistor including a first oxide semiconductor; a second transistor including a second oxide semiconductor; a capacitor element; a first insulator; and a first conductor in contact with a source or a drain of the second transistor. The capacitor element includes a second conductor, a third conductor, and a second insulator. The first transistor, the second transistor, and the first conductor are placed to be embedded in the first insulator. The second conductor is placed in contact with a top surface of the first conductor and a top surface of a gate of the first transistor. The second insulator is placed over the second conductor and the first insulator. The third conductor is placed to cover the second conductor with the second insulator therebetween.
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公开(公告)号：US12080377B2
公开(公告)日：2024-09-03
申请号：US17802281
申请日：2021-03-04
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yuki Okamoto , Tatsuya Onuki , Munehiro Kozuma , Takanori Matsuzaki
IPC: G11C7/10 , G11C7/12 , G11C8/08 , H01L29/786 , H10B12/00
CPC classification number: G11C7/1096 , G11C7/12 , G11C8/08 , H01L29/7869 , H10B12/31 , H10B12/50
Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.
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