公开(公告)号：US20170301623A1

公开(公告)日：2017-10-19

申请号：US15379146

申请日：2016-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Jean-Philippe Escales

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L23/5283 ,  H01L21/31111 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76892 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/528 ,  H01L23/53295

Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.

公开(公告)号：US20170243652A1

公开(公告)日：2017-08-24

申请号：US15218261

申请日：2016-07-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: G11C16/22 ,  H01L27/115 ,  H01L21/311 ,  H01L23/00

CPC classification number: G11C16/22 ,  G06F21/87 ,  H01L21/31116 ,  H01L21/74 ,  H01L21/823481 ,  H01L21/823892 ,  H01L22/14 ,  H01L22/34 ,  H01L23/57 ,  H01L23/576 ,  H01L27/115 ,  H01L29/7846

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

公开(公告)号：US20170207052A1

公开(公告)日：2017-07-20

申请号：US15477876

申请日：2017-04-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Sebastian Orellana

IPC: H01H49/00 ,  H01H59/00

CPC classification number: H01H49/00 ,  H01H59/0009 ,  H01H2001/0052 ,  H01H2001/0057 ,  H01H2001/0078 ,  H01H2061/006 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.

公开(公告)号：US09653392B2

公开(公告)日：2017-05-16

申请号：US14920621

申请日：2015-10-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Sebastian Orellana

IPC: H01L23/522 ,  H01L23/532 ,  H01H59/00 ,  H01H1/00 ,  H01H61/00

CPC classification number: H01H49/00 ,  H01H59/0009 ,  H01H2001/0052 ,  H01H2001/0057 ,  H01H2001/0078 ,  H01H2061/006 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.

公开(公告)号：US20170103980A1

公开(公告)日：2017-04-13

申请号：US15383214

申请日：2016-12-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L27/06 ,  H01G5/16 ,  H01L21/768 ,  H01L23/522 ,  H01L49/02 ,  H01G5/011 ,  H01L23/528

CPC classification number: H01L27/0629 ,  H01G5/011 ,  H01G5/16 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7687 ,  H01L23/4821 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.

公开(公告)号：US20170098615A1

公开(公告)日：2017-04-06

申请号：US15137063

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Jean-Philippe Escales

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228

Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.

公开(公告)号：US09536874B2

公开(公告)日：2017-01-03

申请号：US15077702

申请日：2016-03-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/48 ,  H01L27/06 ,  H01L23/522 ,  H01L21/768 ,  H01G5/16 ,  H01G5/011 ,  H01L23/482 ,  H01L49/02 ,  H01L23/64

CPC classification number: H01L27/0629 ,  H01G5/011 ,  H01G5/16 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7687 ,  H01L23/4821 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.

Abstract translation: 可变电容器包括设置在覆盖在基板上的第一金属层中的固定主电容器电极，与固定主电容器电极间隔开的第二主电容器电极和设置在与固定主电容器电极相邻的第一金属层中的可移动电容器电极。 可以使可动电容电极处于与固定主电容器电极欧姆电连接的第一位置，使得可变电容器具有第一电容值或与固定主电容器电极间隔开的第二位置，使得可变电容器具有 第二电容值。

公开(公告)号：US09324706B2

公开(公告)日：2016-04-26

申请号：US14957544

申请日：2015-12-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L21/02 ,  H01L27/06 ,  H01L23/482 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/64

CPC classification number: H01L27/0629 ,  H01G5/011 ,  H01G5/16 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7687 ,  H01L23/4821 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate. The variable capacitor is formed within a cavity of the back end of line metallization. The variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer of the back end of line metallization, a second main capacitor electrode electrically connected to a second metal layer of the back end of line metallization and vertically spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode.

Abstract translation: 提供一种形成具有设置在金属化中的可变电容器的集成电路芯片的方法。 线路金属化的后端形成在半导体衬底上。 可变电容器形成在线金属化后端的腔内。 可变电容器包括设置在线金属化后端的第一金属层中的固定主电容器电极，电连接到线金属化后端的第二金属层并与固定主电容器垂直间隔的第二主电容器电极 电极和设置在与固定主电容器电极相邻的第一金属层中的可动电容电极。

公开(公告)号：US20160111470A1

公开(公告)日：2016-04-21

申请号：US14979282

申请日：2015-12-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L27/16 ,  H01L35/34 ,  H01L35/02

CPC classification number: H01L27/16 ,  H01L23/38 ,  H01L35/02 ,  H01L35/34 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Method of Wireless Communication using Thermoelectric Generators Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.

Abstract translation: 使用热电发生器的无线通信方法第一设备与第二设备之间的无线通信方法，其中第一设备和第二设备分别包括第一热电发电机和第二热电发电机，两个热电发生器处于热耦合 在第一装置内产生第一信号，第一热电发电机作为第一信号的功能被电力供电，以便在所述第一发生器中产生第一热梯度，并在第二发生器中产生第二热梯度，以及 基于由第二热电发电机响应于所述第二热梯度产生的电能在第二装置内产生第二信号。

公开(公告)号：US20150255540A1

公开(公告)日：2015-09-10

申请号：US14715090

申请日：2015-05-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/06 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66568 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by a trench insulating region. The transistor, active region and trench insulating region are covered by an additional insulating region. A metal contact extends through the additional insulating region to make contact with the trench insulating region. The metal contact may penetrate into the trench insulating region.

Abstract translation: 集成电路包括衬底和至少一个NMOS晶体管，其在衬底中具有由沟槽绝缘区域包围的有源区域。 晶体管，有源区和沟槽绝缘区被额外的绝缘区覆盖。 金属接触件延伸穿过附加绝缘区域以与沟槽绝缘区域接触。 金属接触可能渗入沟槽绝缘区域。