公开(公告)号：US09874856B2

公开(公告)日：2018-01-23

申请号：US14883364

申请日：2015-10-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: G11C16/04 ,  H01L27/115 ,  G04F10/10 ,  G11C16/28 ,  G11C16/34 ,  G11C27/00 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  H01L29/51

CPC classification number: G04F10/10 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/349 ,  G11C27/005 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

公开(公告)号：US09812399B2

公开(公告)日：2017-11-07

申请号：US15137063

申请日：2016-04-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Jean-Philippe Escales

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228

Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.

公开(公告)号：US20170194267A1

公开(公告)日：2017-07-06

申请号：US15466396

申请日：2017-03-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Guilhem Bouton

IPC: H01L23/00 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L23/576 ,  G06F17/5068 ,  H01L21/768 ,  H01L21/76838 ,  H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

公开(公告)号：US09670058B2

公开(公告)日：2017-06-06

申请号：US14501537

申请日：2014-09-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Antonio Di-Giacomo ,  Pascal Fornara

IPC: B81B7/02 ,  G01P13/00 ,  G01P15/135 ,  G01C9/12 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81B7/02 ,  B81B3/0051 ,  B81B2201/0235 ,  B81B2201/0292 ,  B81C1/00174 ,  B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0771 ,  G01C9/12 ,  G01P13/00 ,  G01P15/135

Abstract: An integrated circuit includes a mechanical device for detection of spatial orientation and/or of change in orientation of the integrated circuit. The device is formed in the BEOL and includes an accommodation whose sides include metal portions formed within various metallization levels. A mobile metal component is accommodated within the accommodation. A monitor inside the accommodation defines a displacement area for the metal component and includes electrically conductive elements disposed at the periphery of the displacement area. The component is configured so as to, under the action of the gravity, come into contact with the two electrically conductive elements in response to a given spatial orientation of the integrated circuit. A detector is configured to detect an electrical link passing through the component and the electrically conductive elements.

公开(公告)号：US20160276496A1

公开(公告)日：2016-09-22

申请号：US14963684

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/866 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.

Abstract translation: 本发明涉及一种齐纳二极管，其包括具有第一导电类型的阴极区，形成在具有第二导电类型的半导体衬底的表面上。 齐纳二极管包括形成在阴极区下面的具有第二导电类型的阳极区域。 一个或多个沟槽隔离将阴极和阳极区域与衬底的其余部分隔离。 第一导电区域被配置为当经受足够的电压时，产生垂直于阴极和阳极区域之间的界面的第一电场。 第二导电区域被配置为当经受足够的电压时，产生平行于阴极和阳极区域之间的界面的第二电场。

公开(公告)号：US20160276447A1

公开(公告)日：2016-09-22

申请号：US14963670

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/866

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66106 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

Abstract translation: 本公开涉及一种齐纳二极管，其包括在平行于衬底表面的平面上形成在半导体衬底中的齐纳二极管结，并位于具有第一导电类型的阳极区域和具有第二导电类型的阴极区域之间 ，阴极区域从衬底的表面延伸。 第一导电区域被配置为在向第一导电区域施加第一电压时产生垂直于齐纳二极管结的平面的第一电场，并且第二导电区域被配置为沿着第一导电区域的平面生成第二电场 在向第二导电区施加第二电压时的齐纳二极管结。

公开(公告)号：US20160093696A1

公开(公告)日：2016-03-31

申请号：US14953692

申请日：2015-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L21/763 ,  H01L27/112 ,  H01L21/762

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20160064339A1

公开(公告)日：2016-03-03

申请号：US14829292

申请日：2015-08-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Guilhem Bouton

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L23/576 ,  G06F17/5068 ,  H01L21/768 ,  H01L21/76838 ,  H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

Abstract translation: 集成电路包括其上形成有多个功能块的基板。 至少两个相同的功能块分别设置在集成电路上的两个或更多个不同位置处。 提供了在功能块的附近和/或内部的电活动的虚拟模块，其中至少两个不同的电不活动的虚拟模块包括在相应的邻域和/或至少两个相同功能块的内部。

公开(公告)号：US09263518B2

公开(公告)日：2016-02-16

申请号：US14300663

申请日：2014-06-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L23/522

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66568 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.

Abstract translation: 集成电路包括衬底和至少一个NMOS晶体管，其在衬底中具有由绝缘区域包围的有源区域。 绝缘区域形成为包括至少一个区域，其中绝缘区域具有通过由基板的一部分形成的分离区域彼此分离的两个绝缘区域。

公开(公告)号：US09082609B2

公开(公告)日：2015-07-14

申请号：US13953003

申请日：2013-07-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice Marinet ,  Pascal Fornara

IPC: H01L29/94 ,  H01L27/00 ,  G11C27/02 ,  H01L49/02 ,  G04F10/10

CPC classification number: H01L27/00 ,  G04F10/10 ,  G11C27/024 ,  H01L28/40 ,  H01L28/60

Abstract: An electric charge flow element including, on an insulating support, a stack of a first electrode, of a dielectric layer having at least one portion capable of letting charges flow by tunnel effect, and of a second electrode, wherein at least one of the electrodes is made of undoped polysilicon.

Abstract translation: 一种电荷流动元件，包括在绝缘支撑件上，具有至少一部分能够通过隧道效应使电荷流动的介电层的第一电极的堆叠和第二电极，其中至少一个所述电极 由未掺杂的多晶硅制成。