公开(公告)号：US20240431122A1

公开(公告)日：2024-12-26

申请号：US18623732

申请日：2024-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongjun LEE ,  Kiseok LEE ,  Hyungeun CHOI ,  Keunnam KIM ,  Incheol NAM

IPC: H10B80/00 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device includes a lower chip structure, and an upper chip structure on the lower chip structure. The lower chip structure includes a memory structure, a lower interconnection structure electrically connected to the memory structure, and a lower bonding pad electrically connected to the lower interconnection structure. The upper chip structure includes an upper base, a peripheral transistor on the upper base, a first upper interconnection structure electrically connected to the peripheral transistor, on the upper base, a through-via penetrating through the upper base and electrically connected to the first upper interconnection structure, an upper bonding pad bonded to the lower bonding pad, below the upper base, and an intermediate connection structure electrically connecting the upper bonding pad and the through-via, between the upper base and the lower chip.

公开(公告)号：US20240315010A1

公开(公告)日：2024-09-19

申请号：US18435198

申请日：2024-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin PARK ,  Jongmin KIM ,  Huijung KIM ,  Kiseok LEE ,  Myeongdong LEE

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

Abstract: Provided is a semiconductor device comprising: an active region defined by an element isolation film in a substrate; a word line extending in a first horizontal direction in the substrate; a bit line extending in a second horizontal direction crossing the first horizontal direction on the substrate; an additional pad disposed on the active region; and a buried contact on the additional pad wherein the buried contact is electrically connected to the active region by the additional pad, wherein the additional pad comprises a first surface that overlaps the word line in a vertical direction, and a second surface that is free of overlap with the word line in the vertical direction, and wherein, the first surface meets the second surface at a cusp.

公开(公告)号：US20240306377A1

公开(公告)日：2024-09-12

申请号：US18488229

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin KIM ,  Kiseok LEE ,  Seung-Bo KO ,  Chan-Sic YOON ,  Myeong-Dong LEE

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/01 ,  H10B12/315

Abstract: A semiconductor device including a first active pattern and a second active pattern each extending along a first direction and arranged along a second direction intersecting the first direction each of the first and second active patterns including a central part, a first edge part, and a second edge part, a storage node pad on the first edge part of the first active pattern, and a bit-line node contact on the central part of the first active pattern, wherein a top surface of the bit-line node contact is located at a higher level than a top surface of the storage node pad may be provided.

公开(公告)号：US20240292594A1

公开(公告)日：2024-08-29

申请号：US18384407

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SangHyun LEE ,  Kiseok LEE ,  Seokhan PARK ,  Sung-Min PARK ,  Iljae SHIN ,  Dongjun LEE ,  Jinwoo HAN

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor memory device includes a semiconductor substrate; a stack structure that includes word lines and interlayer dielectric patterns that are alternately stacked on the semiconductor substrate; an etch stop layer on the stack structure; semiconductor patterns that penetrate the word lines; a bit line in contact with the semiconductor patterns; capping dielectric patterns between the bit line and the word lines, the capping dielectric patterns covering sidewalls of the word lines; and a data storage element on the semiconductor substrate, wherein a level of a bottom surface of the etch stop layer is the same as a level of a top surface of the data storage element.

公开(公告)号：US20240290833A1

公开(公告)日：2024-08-29

申请号：US18537552

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho CHOI ,  Kiseok LEE ,  Chansic YOON ,  Jaybok CHOI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/7855 ,  H10B12/482

Abstract: A semiconductor device includes device isolation layers extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction, active regions between the device isolation layers and spaced apart from each other in the first horizontal direction, insulating structures between the active regions, and a gate structure extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the active regions, wherein two side surfaces of each active region adjacent to each other define an acute angle, and wherein at least a portion of at least one of the insulating structures is between a corresponding pair of the active regions and between a corresponding pair of the device isolation layers and overlaps the corresponding pair of the active regions in the first horizontal direction.

公开(公告)号：US20240266408A1

公开(公告)日：2024-08-08

申请号：US18507224

申请日：2023-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM

IPC: H01L29/417 ,  H01L27/088

CPC classification number: H01L29/41741 ,  H01L27/088

Abstract: A semiconductor device includes a device isolation part on a substrate and defining active regions that are two-dimensionally disposed in first and second directions, the active regions each extending in the first direction; first and second word lines crossing the active regions in the second direction and adjacent to each other in the first direction; a first impurity region in the active region between the first and second word lines; a second impurity region in the active region at one side of the first word line and spaced apart from the first impurity region; a first conductive pad in contact with the first impurity region; a second conductive pad in contact with the second impurity region; a bit line on the first conductive pad and extending in the first direction; a storage node contact structure on the second conductive pad; and a landing pad on the storage node contact structure.

公开(公告)号：US20240147707A1

公开(公告)日：2024-05-02

申请号：US18242817

申请日：2023-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taegyu KANG ,  Taehyuk KIM ,  Seok-Ho SHIN ,  Keunnam KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Kiseok LEE

IPC: H10B12/00 ,  H01L23/522

CPC classification number: H10B12/50 ,  H01L23/5225 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, an active pattern on the cell array region of the substrate, a peripheral active pattern on the peripheral circuit region of the substrate, a peripheral gate electrode disposed on a top surface of the peripheral active pattern, a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, and a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region. In the cell array region, the second interlayer insulating pattern may have a top surface, which is located at substantially the same level as a top surface of the first etch stop layer.

公开(公告)号：US20240098984A1

公开(公告)日：2024-03-21

申请号：US18368243

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungeun CHOI ,  Seokho SHIN ,  Joongchan SHIN ,  Kiseok LEE ,  Keunnam KIM ,  Seokhan PARK ,  Eunsuk JANG ,  Jinwoo HAN

IPC: H10B12/00 ,  H01L29/78

CPC classification number: H10B12/482 ,  H01L29/7827 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device may include a substrate, a bitline extending in a first direction on the substrate, and an active pattern on the bitline. The semiconductor device may include a back gate electrode extending beside one side of the active pattern in a second direction perpendicular to the first direction across the bitline, and a wordline extending in the second direction beside the other side of the active pattern. A length of the active pattern in the second direction may be greater than a length of the bitline in the second direction.

公开(公告)号：US20230422486A1

公开(公告)日：2023-12-28

申请号：US18109442

申请日：2023-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Jongmin KIM ,  Hyo-Sub KIM ,  Hui-Jung KIM ,  Sohyun PARK ,  Junhyeok AHN ,  Chan-Sic YOON ,  Myeong-Dong LEE ,  Woojin JEONG ,  Wooyoung CHOI

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/34 ,  H10B12/053 ,  H10B12/485

Abstract: A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

公开(公告)号：US20230180452A1

公开(公告)日：2023-06-08

申请号：US17956102

申请日：2022-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Taegyu KANG ,  Keunnam KIM ,  Sung-Min PARK ,  Taehyun AN ,  Sanghyun LEE ,  Eunsuk JANG ,  Moonyoung JEONG ,  Euichul JEONG ,  Hyungeun CHOI

IPC: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

CPC classification number: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.