公开(公告)号：US20170052415A1

公开(公告)日：2017-02-23

申请号：US15344795

申请日：2016-11-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Kouhei TOYOTAKA ,  Masahiko HAYAKAWA ,  Daisuke MATSUBAYASHI ,  Shinpei MATSUDA

IPC: G02F1/1343 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1362

CPC classification number: G02F1/134309 ,  G02F1/133345 ,  G02F1/1343 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The following semiconductor device provides high reliability and a narrower frame width. The semiconductor device includes a driver circuit and a pixel portion. The driver circuit has a first transistor including a first gate and a second gate electrically connected to each other with a semiconductor film sandwiched therebetween, and a second transistor electrically connected to the first transistor. The pixel portion includes a third transistor, a liquid crystal element, and a capacitor. The liquid crystal element includes a first transparent conductive film electrically connected to the third transistor, a second conductive film, and a liquid crystal layer. The capacitor includes the first conductive film, a third transparent conductive film, and a nitride insulating film. The nitride insulating film is positioned between the first transparent conductive film and the third transparent conductive film, and positioned between the semiconductor film and the second gate of the first transistor.

Abstract translation: 以下半导体器件提供高可靠性和较窄的帧宽度。 半导体器件包括驱动电路和像素部分。 驱动电路具有包括第一栅极和第二栅极的第一晶体管，其中夹在其间的半导体膜彼此电连接，第二晶体管与第一晶体管电连接。 像素部分包括第三晶体管，液晶元件和电容器。 液晶元件包括与第三晶体管电连接的第一透明导电膜，第二导电膜和液晶层。 电容器包括第一导电膜，第三透明导电膜和氮化物绝缘膜。 氮化物绝缘膜位于第一透明导电膜和第三透明导电膜之间，位于第一晶体管的半导体膜和第二栅极之间。

公开(公告)号：US20170005126A1

公开(公告)日：2017-01-05

申请号：US15193677

申请日：2016-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Riho KATAISHI ,  Hiroshi OHKI ,  Yuichi SATO ,  Daisuke MATSUBAYASHI

IPC: H01L27/146 ,  H01L31/109 ,  H01L31/0296 ,  H01L31/0224 ,  H01L31/0272

CPC classification number: H01L27/14607 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14647 ,  H01L27/14665 ,  H01L27/14694 ,  H01L27/14696 ,  H01L31/0224 ,  H01L31/022475 ,  H01L31/0272 ,  H01L31/0296 ,  H01L31/032 ,  H01L31/109

Abstract: An imaging device with excellent imaging performance is provided. An imaging device that easily performs imaging under a low illuminance condition is provided. A low power consumption imaging device is provided. An imaging device with small variations in characteristics between its pixels is provided. A highly integrated imaging device is provided. A photoelectric conversion element includes a first electrode, and a first layer, a second layer, and a third layer. The first layer is provided between the first electrode and the third layer. The second layer is provided between the first layer and the third layer. The first layer contains selenium. The second layer contains a metal oxide. The third layer contains a metal oxide and also contains at least one of a rare gas atom, phosphorus, and boron. The selenium may be crystalline selenium. The second layer may be a layer of an In—Ga—Zn oxide including c-axis-aligned crystals.

Abstract translation: 提供了具有出色成像性能的成像装置。 提供了在低照度条件下容易进行成像的成像装置。 提供了一种低功耗成像装置。 提供了其像素之间的特性变化小的成像装置。 提供了高度集成的成像装置。 光电转换元件包括第一电极和第一层，第二层和第三层。 第一层设置在第一电极和第三层之间。 第二层设置在第一层和第三层之间。 第一层含硒。 第二层含有金属氧化物。 第三层包含金属氧化物，并且还含有稀有气体原子，磷和硼中的至少一种。 硒可以是结晶硒。 第二层可以是包括c轴对准晶体的In-Ga-Zn氧化物层。

公开(公告)号：US20160380108A1

公开(公告)日：2016-12-29

申请号：US15262547

申请日：2016-09-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Keisuke MURAYAMA

IPC: H01L29/786 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/7831

Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

公开(公告)号：US20160335979A1

公开(公告)日：2016-11-17

申请号：US15223659

申请日：2016-07-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiroyuki MIYAKE ,  Daisuke MATSUBAYASHI

IPC: G09G3/36 ,  H01L27/12

CPC classification number: G09G3/3696 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/043 ,  G09G2310/0286 ,  G09G2320/0214 ,  G09G2330/00 ,  H01L27/1225 ,  H01L27/124

Abstract: To prevent an influence of normally-on characteristics of the transistor which a clock signal is input to a terminal of, a wiring to which a first low power supply potential is applied and a wiring to which a second low power supply potential lower than the first low power supply potential is applied are electrically connected to a gate electrode of the transistor. A semiconductor device including the transistor can operate stably.

Abstract translation: 为了防止输入时钟信号的晶体管的常开特性对施加第一低电源电位的布线和低于第一低电源电位的第二低电源电位的布线的端子的影响 低电源电位被施加电连接到晶体管的栅电极。 包括晶体管的半导体器件可以稳定地工作。

公开(公告)号：US20160329436A1

公开(公告)日：2016-11-10

申请号：US15214689

申请日：2016-07-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KOBAYASHI ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869

Abstract: A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.

公开(公告)号：US20160307901A1

公开(公告)日：2016-10-20

申请号：US15193189

申请日：2016-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daisuke MATSUBAYASHI

IPC: H01L27/105 ,  H01L29/786 ,  H01L23/528 ,  H01L27/06 ,  H01L27/12

CPC classification number: H01L27/1052 ,  G11C8/10 ,  G11C11/404 ,  G11C11/405 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869

Abstract: A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.

Abstract translation: 对各个存储单元执行选择操作。 一种器件包括与第一存储器单元相同的行中提供的第一存储单元和第二存储单元，每个存储单元包括具有第一栅极和第二栅极的场效应晶体管。 场效应晶体管通过导通或截止来控制存储单元中的至少数据写入和数据保持。 该装置还包括电连接到包括在第一存储单元和第二存储单元中的场效应晶体管的第一栅极的行选择线，电连接到场效应晶体管的第二栅极的第一列选择线 以及与第二存储单元中包含的场效应晶体管的第二栅极电连接的第二列选择线。

公开(公告)号：US20160254371A1

公开(公告)日：2016-09-01

申请号：US15150587

申请日：2016-05-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi KOEZUKA ,  Yukinori SHIMA ,  Hajime TOKUNAGA ,  Toshinari SASAKI ,  Keisuke MURAYAMA ,  Daisuke MATSUBAYASHI

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L29/66969 ,  H01L21/022 ,  H01L21/02263 ,  H01L27/1225 ,  H01L29/513 ,  H01L29/78609 ,  H01L29/7869

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

Abstract translation: 为了减少半导体器件中的氧化物半导体膜的缺陷。 为了改善包括氧化物半导体膜的半导体器件的电特性和可靠性。 在包括晶体管的半导体器件中，所述晶体管包括形成在衬底上的栅电极，覆盖栅电极的栅极绝缘膜，与栅电极重叠的多层膜，栅极绝缘膜设置在其间;以及一对电极， 多层膜，覆盖晶体管的第一氧化物绝缘膜和形成在第一氧化物绝缘膜上的第二氧化物绝缘膜，多层膜包括氧化物半导体膜和含有In或Ga的氧化物膜，第一氧化物绝缘膜为 氧透过氧化物绝缘膜，第二氧化物绝缘膜是比化学计量组合物含有氧更多的氧化物绝缘膜。

公开(公告)号：US20160190338A1

公开(公告)日：2016-06-30

申请号：US14976474

申请日：2015-12-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tetsuhiro TANAKA ,  Daisuke MATSUBAYASHI ,  Kazuki TANEMURA

IPC: H01L29/786 ,  H01L21/479 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L21/479 ,  H01L27/1225 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42384 ,  H01L29/66833 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/7883 ,  H01L29/792

Abstract: To provide a semiconductor device suitable for high reliability and high-speed operation. The semiconductor device includes a first conductor, a first insulator, a second insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The first conductor includes a region overlapping with the channel formation region with the first insulator provided therebetween. The second insulator is placed to include a region in contact with a side surface of the first conductor. The electron trap layer is placed to face the first conductor with the second insulator provided therebetween.

Abstract translation: 提供适用于高可靠性和高速运行的半导体器件。 半导体器件包括第一导体，第一绝缘体，第二绝缘体，半导体和电子陷阱层。 半导体包括沟道形成区域。 第一导体包括与沟道形成区重叠的区域，其间设置有第一绝缘体。 第二绝缘体被放置成包括与第一导体的侧表面接触的区域。 电子陷阱层被放置为面对第一导体，其间设置有第二绝缘体。

公开(公告)号：US20150200305A1

公开(公告)日：2015-07-16

申请号：US14593227

申请日：2015-01-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KOBAYASHI ,  Daisuke MATSUBAYASHI

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869

Abstract: A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.

Abstract translation: 本发明的一个实施例的半导体器件包括半导体，绝缘体，第一导体和第二导体。 在半导体器件中，半导体的顶表面具有与绝缘体接触的区域; 半导体的侧面具有与绝缘体接触的区域; 第一导体具有与半导体重叠的第一区域，绝缘体位于它们之间; 第一区域具有与半导体的顶表面接触的区域和与半导体的侧表面接触的区域; 所述第二导体具有与所述半导体接触的第二区域; 并且第一区域和第二区域彼此不重叠。

公开(公告)号：US20150179804A1

公开(公告)日：2015-06-25

申请号：US14617308

申请日：2015-02-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Daisuke MATSUBAYASHI ,  Yutaka OKAZAKI

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78696

Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10−5 Ω·m or more and 4.8×10−3 Ω·m or less.

Abstract translation: 半导体器件包括具有沟道形成区域的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管。 在晶体管中，沟道长度小（5nm以上且小于60nm，优选为10nm以上且40nm以下），栅极绝缘膜的厚度大（通过以下方式获得的等效氧化物厚度 转化成含有氮的氧化硅的厚度为5nm以上且50nm以下，优选为10nm以上至40nm以下。 或者，通道长度小（5nm以上且小于60nm，优选为10nm以上且40nm以下），源极区域和漏极区域的电阻率为1.9×10-5＆OHgr· m以上4.8×10-3＆OHgr·m以下。