公开(公告)号：US07356713B2

公开(公告)日：2008-04-08

申请号：US10631537

申请日：2003-07-31

申请人： Shigehiro Asano ,  Jeffrey Douglas Brown ,  Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Alvan Wing Ng ,  Michael Fan Wang ,  Thuong Quang Truong

发明人： Shigehiro Asano ,  Jeffrey Douglas Brown ,  Michael Norman Day ,  Charles Ray Johns ,  James Allan Kahle ,  Alvan Wing Ng ,  Michael Fan Wang ,  Thuong Quang Truong

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F12/0831 ,  G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops.

摘要翻译： 基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。 然后，当侦听请求发生时，响应于窥探请求发送重试协议。 结合重试协议，发送信号使组件进入窥探模式。 当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。 在snoop请求已满足后，组件再次进入低功耗模式。 因此，该组件能够在两个snoops之间进入低功耗模式。

公开(公告)号：US06611870B1

公开(公告)日：2003-08-26

申请号：US09136513

申请日：1998-08-19

申请人： Shigehiro Asano ,  Tatsunori Kanai ,  Shinichi Kanno ,  Seiji Maeda

发明人： Shigehiro Asano ,  Tatsunori Kanai ,  Shinichi Kanno ,  Seiji Maeda

IPC分类号： G06F1516

CPC分类号： G06F13/385

摘要： A server device and a communication connection scheme capable of expanding the memory bandwidth and thereby expanding the power to transmit Web data to the network are disclosed. Network cards are detachably attached to a host machine (main machine). Each network card contains a processor, a memory, and a network interface unit, where data are transmitted to the network from a memory on the network card and the memory bandwidth expansion is realized by the presence of a plurality of network cards. In addition, using a memory of the network card as a cache, the load on the host machine is reduced by transmitting data from this memory to the network when the data exists on the memory and a certain condition is satisfied.

摘要翻译： 公开了能够扩展存储器带宽并由此扩展将网络数​​据传输到网络的功能的服务器设备和通信连接方案。 网卡可拆卸地连接到主机（主机）。 每个网卡包含处理器，存储器和网络接口单元，其中数据从网卡上的存储器发送到网络，并且通过存在多个网卡来实现存储器带宽扩展。 此外，使用网卡的存储器作为缓存，当数据存在于存储器上并且满足一定条件时，通过从该存储器向网络发送数据来减少主机上的负载。

公开(公告)号：US06295560B1

公开(公告)日：2001-09-25

申请号：US09205368

申请日：1998-12-04

申请人： Shinichi Kanno ,  Shigehiro Asano

发明人： Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G06F1300

CPC分类号： G06F9/5083

摘要： A data delivery system capable of distributing processing loads on the data supply side without providing the control processor, in which clients can receive data delivery without becoming conscious of the switching of processors that carry out the data delivery, is disclosed. In this data delivery system, a request from the client to the data delivery system is always received by all the data delivery units according to the shared lower layer address, while a response to the connection request is made by only one data delivery unit which has the response right at that moment using the unique lower layer address of that data delivery unit. In this way, it appears to the client as if the request is always made with respect to the same correspondent, while at the data supply side, the data delivery unit for responding to the client is appropriately switched by appropriately transferring the response right so as to realize the load distribution within the data delivery system.

摘要翻译： 公开了一种能够在不提供控制处理器的情况下在数据提供侧分配处理负荷的数据传送系统，其中客户端可以在不意识到进行数据传送的处理器的切换的情况下接收数据传送。 在该数据传送系统中，由所有数据传送单元总是按照共享的下层地址接收来自客户端到数据传送系统的请求，而对连接请求的响应仅由一个数据传送单元进行， 此时使用该数据传送单元的唯一下层地址的响应权限。 以这种方式，对于客户端来说，似乎总是针对相同的记者进行请求，而在数据提供端，通过适当地转移响应权来适当地切换用于响应客户端的数据传送单元，以便 实现数据传送系统内的负载分配。

公开(公告)号：US5862403A

公开(公告)日：1999-01-19

申请号：US603759

申请日：1996-02-16

申请人： Tatsunori Kanai ,  Shigehiro Asano ,  Takeshi Aikawa ,  Shinya Amano

发明人： Tatsunori Kanai ,  Shigehiro Asano ,  Takeshi Aikawa ,  Shinya Amano

IPC分类号： G06F3/06 ,  G06F11/10 ,  H04L12/54 ,  H04L12/861 ,  H04L12/883 ,  G06F15/02

CPC分类号： H04L12/5693 ,  G06F11/1076 ,  G06F11/1088 ,  G06F3/0601 ,  H04L49/90 ,  H04L49/9021 ,  H04L49/9047 ,  H04L49/9073 ,  G06F2003/0692

摘要： A continuous data server apparatus incorporating a plurality of buffer memory units for storing the continuous data read out by the data memory control units and to be given to the communication control unit, at least one buffer memory unit being provided dedicatedly for each combination of one data memory control unit group formed by at least one data memory control unit and one communication control unit group formed by at least one communication control unit. The apparatus may further incorporate a plurality of calculation units connected in series, where each calculation unit is connected between corresponding one data memory control unit group and at least one buffer memory unit, and carrying out a prescribed calculation processing. The continuous data can be arranged over a plurality of data memory control units in word units, such that the data memory control units read out the continuous data in block units, the buffer memory units store the continuous data in block units, and the communication control unit transfers the continuous data obtained by reading out data the buffer memory units sequentially in word units.

摘要翻译： 一种连续数据服务器装置，其包括多个缓冲存储器单元，用于存储由数据存储器控制单元读出的连续数据，并被提供给通信控制单元，至少一个缓冲存储器单元专门为一个数据的每个组合提供 由至少一个数据存储器控制单元形成的存储器控​​制单元组和由至少一个通信控制单元形成的一个通信控制单元组。 该装置还可以包括串联连接的多个计算单元，其中每个计算单元连接在相应的一个数据存储器控制单元组和至少一个缓冲存储器单元之间，并执行规定的计算处理。 连续数据可以以单位单位布置在多个数据存储器控制单元上，使得数据存储器控制单元以块为单位读出连续数据，缓冲存储器单元以块为单位存储连续数据，并且通信控制 单元通过以字为单位顺序地读出缓冲存储器单元的数据而获得的连续数据。

公开(公告)号：US08555027B2

公开(公告)日：2013-10-08

申请号：US13038845

申请日：2011-03-02

申请人： Tetsuro Kimura ,  Shigehiro Asano

发明人： Tetsuro Kimura ,  Shigehiro Asano

IPC分类号： G06F9/26 ,  G06F9/34

CPC分类号： G06F11/108 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7208

摘要： According to one embodiment, a semiconductor memory controlling device includes a write control unit that writes a predetermined number of pieces of first data and redundant information calculated by using the predetermined number of pieces of the first data and used for correcting an error in the first data into different semiconductor storage drives, respectively; a constructing unit that constructs a storage area for storing therein a table by using driver information, the table showing an association between a logical address and a physical address of the first data and identification information for associating the predetermined number of pieces of first data with the redundant information; and a table controlling unit that stores, into the storage area, the table associated with the identification information, the physical address and the logical address of the predetermined number of pieces of the first data, and a physical address of the redundant information.

摘要翻译： 根据一个实施例，半导体存储器控制装置包括：写入控制单元，其写入预定数量的第一数据和通过使用预定数量的第一数据计算的冗余信息，并用于校正第一数据中的错误 分别进入不同的半导体存储驱动器; 构建单元，其通过使用驾驶员信息构建用于在其中存储表的存储区域，表示第一数据的逻辑地址和物理地址之间的关联的表以及用于将预定数量的第一数据与 冗余信息; 以及表控制单元，其向存储区域存储与识别信息相关联的表，预定数量的第一数据的物理地址和逻辑地址以及冗余信息的物理地址。

公开(公告)号：US08549388B2

公开(公告)日：2013-10-01

申请号：US13035194

申请日：2011-02-25

申请人： Kazuhiro Fukutomi ,  Hiroshi Yao ,  Shinichi Kanno ,  Shigehiro Asano ,  Toshikatsu Hida ,  Yasuhiro Kimura

发明人： Kazuhiro Fukutomi ,  Hiroshi Yao ,  Shinichi Kanno ,  Shigehiro Asano ,  Toshikatsu Hida ,  Yasuhiro Kimura

IPC分类号： H03M13/00

CPC分类号： G06F11/108 ,  G06F2211/1059 ,  G06F2211/1073 ,  G06F2211/1092

摘要： According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.

摘要翻译： 根据一个实施例，控制器控制对包括第一数据存储单元和第二数据存储单元的存储装置的写入和读取。 第二数据存储单元存储用户数据和用户数据的奇偶校验数据。 第一数据存储单元存储奇偶校验数据。 控制器包括奇偶校验更新单元和奇偶校验写入单元。 当更新奇偶校验数据时，奇偶校验更新单元将更新的奇偶校验数据写入第一数据存储单元。 当满足特定要求时，奇偶写入单元读取写入第一数据存储单元中的奇偶校验数据，并将读出的奇偶校验数据写入第二数据存储单元。

公开(公告)号：US20130238838A1

公开(公告)日：2013-09-12

申请号：US13603989

申请日：2012-09-05

申请人： Kazuhiro FUKUTOMI ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kazuhiro FUKUTOMI ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0859 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0873 ,  G06F2212/604 ,  G06F2212/7202 ,  G06F2212/7203

摘要： According to an embodiment, a controller is connected to an external storage device and controls access to a semiconductor storage device including blocks each including memory cell groups each having memory cells. The block includes pages associated with each memory cell group. A writing process for each memory cell group includes writing stages. The controller includes a determining unit configured to determine data to be transferred to the page required in the writing process for a first memory cell group before the writing stage first starts when the writing stage is performed; a reading unit configured to read the determined data from the semiconductor storage device and to store the read data in the external storage device before the writing stage starts; and a writing unit configured to perform the writing process using the data stored in the external storage device when the writing stage is performed.

摘要翻译： 根据实施例，控制器连接到外部存储装置，并且控制对包括各自包含存储单元的存储单元组的块的半导体存储装置的访问。 该块包括与每个存储器单元组相关联的页面。 每个存储单元组的写入过程包括写入阶段。 控制器包括：确定单元，被配置为在执行写入阶段时，在写入阶段首先开始之前，确定要传送到第一存储单元组的写入处理所需的页面的数据; 读取单元，其被配置为从所述半导体存储装置读取所确定的数据，并且在所述写入阶段开始之前将读取的数据存储在所述外部存储装置中; 以及写入单元，被配置为当执行写入阶段时，使用存储在外部存储装置中的数据执行写入处理。

公开(公告)号：US08453033B2

公开(公告)日：2013-05-28

申请号：US12885962

申请日：2010-09-20

申请人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： H03M13/09

CPC分类号： G06F11/1048

摘要： According to one embodiment, a semiconductor memory device includes semiconductor memory chips having writable storage regions in which data is written. The data has one or more pieces of first data, and one or more pieces of the first data includes second data. The device includes a determining unit that determines a prescribed number or fewer of semiconductor memory chips to which the first data is written; a write controller that writes the the first data and redundant information calculated from the second data and used for correcting an error in the second data into the writable storage regions in the determined semiconductor memory chips; and a storage unit that stores identification information and region specifying information associated with each other. The identification information associates the second data and the redundant information, and the region specifying information specifies the storage regions in the semiconductor memory chips to which the first data included in the second data and the redundant information are written.

摘要翻译： 根据一个实施例，半导体存储器件包括具有可写入存储区域的数据被写入的半导体存储器芯片。 数据具有一个或多个第一数据，并且一个或多个第一数据包括第二数据。 该装置包括：确定单元，其确定写入第一数据的半导体存储器芯片的规定数量以下; 写入控制器，其将从第二数据计算出的第一数据和冗余信息写入第二数据中的错误，并将其写入到所确定的半导体存储器芯片中的可写入存储区域中; 以及存储单元，其存储彼此相关联的识别信息和区域指定信息。 所述识别信息将所述第二数据和所述冗余信息相关联，并且所述区域指定信息指定在所述第二数据中包含的所述第一数据和所述冗余信息被写入的所述半导体存储器芯片中的存储区域。

公开(公告)号：US08392476B2

公开(公告)日：2013-03-05

申请号：US12885941

申请日：2010-09-20

申请人： Shigehiro Asano ,  Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno

发明人： Shigehiro Asano ,  Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno

IPC分类号： G06F17/30

CPC分类号： G06F12/0246 ,  G06F2212/7205

摘要： According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.

摘要翻译： 根据一个实施例，半导体存储器件响应于从主机以指定的逻辑块地址写入数据的请求，执行将数据写入到半导体存储器元件，并且执行将有效数据写入半导体存储元件以进行压缩 以日志结构的方式。 半导体存储器装置根据预定的比例调整来自主机的请求的写入响应的频率和用于压缩的写入频率。

公开(公告)号：US08341497B2

公开(公告)日：2012-12-25

申请号：US12713631

申请日：2010-02-26

申请人： Kazuhiro Fukutomi ,  Hideaki Sato ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kazuhiro Fukutomi ,  Hideaki Sato ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G06F11/108 ,  G06F11/1052

摘要： A semiconductor storage includes a receiver configured to receive a write request from a host device; a storage unit configured to hold redundancy data generation/non-generation information; a writing unit configured to write data in a semiconductor memory array and write redundancy data generation/non-generation information of the written data in the storage unit; a first data extracting unit configured to extract data whose redundancy data is not generated from among the data held by the semiconductor memory array; a first redundancy data generating unit configured to generate redundancy data; a first redundancy data writing unit configured to write the generated redundancy data in the semiconductor memory array; and a first redundancy data generation/non-generation information updating unit configured to update the redundancy data generation/non-generation information of the data whose redundancy data held by the storage unit is generated.

摘要翻译： 半导体存储器包括被配置为从主机设备接收写请求的接收器; 存储单元，被配置为保存冗余数据生成/非生成信息; 写入单元，被配置为在半导体存储器阵列中写入数据，并将写入的数据的冗余数据生成/非生成信息写入存储单元中; 第一数据提取单元，被配置为从半导体存储器阵列保存的数据中提取不产生冗余数据的数据; 第一冗余数据生成单元，被配置为生成冗余数据; 第一冗余数据写入单元，被配置为将所生成的冗余数据写入所述半导体存储器阵列中; 以及第一冗余数据生成/非生成信息更新单元，被配置为更新由所述存储单元保持的冗余数据生成的数据的冗余数据生成/非生成信息。