公开(公告)号：US11727989B2

公开(公告)日：2023-08-15

申请号：US17734807

申请日：2022-05-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L29/788 ,  H10B41/30 ,  G06N3/045

CPC classification number: G11C16/0425 ,  G06N3/08 ,  H01L29/7883 ,  H01L29/7885 ,  H10B41/30 ,  G06N3/045

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. In one example, a method for programming a plurality of non-volatile memory cells in an array of non-volatile memory cells, comprises generating a high voltage, and programming a plurality of non-volatile memory cells in an array using the high voltage when a programming enable signal is asserted and providing a feedback loop to maintain the high voltage while programming the plurality of non-volatile memory cells.

公开(公告)号：US11646078B2

公开(公告)日：2023-05-09

申请号：US17199243

申请日：2021-03-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Stanley Hong ,  Feng Zhou ,  Xian Liu ,  Nhan Do

IPC: G11C7/22 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/003 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2013/0066 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/79 ,  G11C2213/82 ,  H10B63/30 ,  H10N70/821 ,  H10N70/8418 ,  H10N70/8833

Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.

公开(公告)号：US11532354B2

公开(公告)日：2022-12-20

申请号：US17024410

申请日：2020-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G06N3/063 ,  G11C16/10

Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.

公开(公告)号：US20220374699A1

公开(公告)日：2022-11-24

申请号：US17875281

申请日：2022-07-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G11C11/54 ,  G06F1/03 ,  G06F17/16 ,  G11C11/56 ,  G06F11/16 ,  G11C13/00 ,  G11C29/44 ,  G06F7/78

Abstract: Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. In one example, a neuron output circuit for providing a current to program as a weight value in a selected memory cell in a vector-by-matrix multiplication array is disclosed, the neuron output circuit comprising a first adjustable current source to generate a scaled current in response to a neuron current to implement a positive weight, and a second adjustable current source to generate a scaled current in response to a neuron current to implement a negative weight.

公开(公告)号：US11373707B2

公开(公告)日：2022-06-28

申请号：US16417518

申请日：2019-05-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/32

Abstract: A non-volatile memory device is disclosed. The non-volatile memory device comprises an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells, and a row driver selectively coupled to a first row and a second row.

公开(公告)号：US11316024B2

公开(公告)日：2022-04-26

申请号：US17165934

申请日：2021-02-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Xian Liu ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: G11C11/34 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04

Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.

公开(公告)号：US20220093623A1

公开(公告)日：2022-03-24

申请号：US17151944

申请日：2021-01-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Guo Xiang Song ,  Leo Xing ,  Jack Sun ,  Xian Liu ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28 ,  H01L21/265 ,  H01L21/762 ,  H01L29/66

Abstract: A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.

公开(公告)号：US11270763B2

公开(公告)日：2022-03-08

申请号：US16382045

申请日：2019-04-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  H01L27/11521 ,  H01L29/423 ,  G11C16/04 ,  G06N3/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/788

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

公开(公告)号：US20220004860A1

公开(公告)日：2022-01-06

申请号：US17140924

申请日：2021-01-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/406

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.

公开(公告)号：US20210305264A1

公开(公告)日：2021-09-30

申请号：US17069563

申请日：2020-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11529 ,  H01L27/11551 ,  H01L29/66 ,  H01L29/423

Abstract: Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.