公开(公告)号：US06277543B1

公开(公告)日：2001-08-21

申请号：US09369412

申请日：1999-08-05

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： G03C500

CPC分类号： G03F7/70466 ,  G03F7/038 ,  G03F7/2022 ,  H01L21/0274

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the “loops” formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.

摘要翻译： 本发明的优选实施例通过提供使用混合抗蚀剂形成不连接特征的方法来克服现有技术的局限性。 该方法使用修剪工艺来修剪由混合抗蚀剂形成的“环”的连接特征。 这允许该方法形成多个未链接的特征而不是循环。 为了修剪端部，通过第二曝光步骤或通过利用灰度光罩，形成与窄特征线相邻的相对较大的修整区域。 更宽或更宽的开放区域允许在窄特征线中形成特征并且从相对较大的区域修剪特征，从而导致区域特征而不是环。

公开(公告)号：US06207493B1

公开(公告)日：2001-03-27

申请号：US09136586

申请日：1998-08-19

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Thomas S. Kanarsky

IPC分类号： H01L218242

CPC分类号： H01L27/10885 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/268 ,  H01L21/743 ,  H01L27/10876

摘要： The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

公开(公告)号：US6114725A

公开(公告)日：2000-09-05

申请号：US93928

申请日：1998-06-09

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

IPC分类号： H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L31/62

CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

公开(公告)号：US6100172A

公开(公告)日：2000-08-08

申请号：US182173

申请日：1998-10-29

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/768 ,  H01L21/822 ,  H01L29/78 ,  H01L21/22 ,  H01L21/425 ,  H01L21/8234

CPC分类号： H01L29/66613 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/76895 ,  H01L21/822 ,  H01L29/7835

摘要： The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

摘要翻译： 本发明提供一种用于在水平表面上形成自对准间隔物的方法，同时从垂直表面移除间隔物材料。 优选的方法使用可以通过使用植入物使其不溶于显影剂的抗蚀剂。 通过在具有垂直和水平表面的基底上保形地沉积抗蚀剂，植入抗蚀剂并显影抗蚀剂，在保持在水平表面上的同时将抗蚀剂从垂直表面上除去。 因此，当从垂直表面移除间隔物材料时，在水平表面上形成自对准间隔物。 然后可以将该水平表面间隔件用于进一步制造。 优选的方法可以用于许多不同的工艺，其中存在需要对衬底的垂直和水平表面进行差异化处理。

公开(公告)号：US20080165335A1

公开(公告)日：2008-07-10

申请号：US12051572

申请日：2008-03-19

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Peter H. Mitchell

IPC分类号： G03B27/42

CPC分类号： G03F7/70341

摘要： An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.

摘要翻译： 公开了一种浸没式光刻设备和方法以及平版印刷光学柱结构，用于在相同压力下用不同流体中的光学系统和晶片的至少投影光学器件进行浸没光刻。 特别地，提供了一种浸没式光刻设备，其中超临界流体被引入晶片周围，并且另一种流体（例如惰性气体）在相同的压力下被引入光学系统的至少投影光学器件以减轻需要 用于特殊镜头。 此外，本发明包括浸没式光刻设备，其包括填充有超临界浸没流体的腔室并且封装要暴露的晶片和至少光学系统的投影光学部件。

公开(公告)号：US20070296937A1

公开(公告)日：2007-12-27

申请号：US11426458

申请日：2006-06-26

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Peter H. Mitchell

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Peter H. Mitchell

IPC分类号： G03B27/42

CPC分类号： G03B27/42 ,  G03F7/70341 ,  G03F7/7085 ,  G03F7/70916

摘要： Embodiments of the invention present a system, method, etc. for illumination light in an immersion lithography stepper for particle or bubble detection. More specifically, embodiments herein provide an immersion lithography expose system comprising a wafer holder for holding a wafer, an immersion liquid for covering the wafer, an immersion head to dispense and contain said immersion liquid, and a light source adapted to lithographically expose a resist on the wafer. The system also comprises a light detector at a first location of the immersion head and a laser source at a second location within said immersion head.

摘要翻译： 本发明的实施例在用于颗粒或气泡检测的浸没式光刻步进机中提供照明光的系统，方法等。 更具体地，本文的实施例提供了浸没式光刻曝光系统，其包括用于保持晶片的晶片保持器，用于覆盖晶片的浸没液体，用于分配和容纳所述浸没液体的浸没头，以及适于光刻曝光抗蚀剂的光源 晶圆。 该系统还包括在浸没头的第一位置处的光检测器和位于所述浸没头内的第二位置处的激光源。

公开(公告)号：US06891226B2

公开(公告)日：2005-05-10

申请号：US10448729

申请日：2003-05-30

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H. Ma

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66484 ,  H01L21/2807 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78648

摘要： The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack.

摘要翻译： 本发明的特征在于双栅极或双栅极逻辑器件，其包含一致的自对准并且具有恒定宽度的沟道的栅极导体。 采用单晶硅晶片作为通道材料。 自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。 通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。

公开(公告)号：US06759315B1

公开(公告)日：2004-07-06

申请号：US09224759

申请日：1999-01-04

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L218238

CPC分类号： H01L21/76897 ,  H01L21/76888 ,  H01L21/76895

摘要： A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.

摘要翻译： 在晶体管中形成修整栅极的方法包括以下步骤：在半导体衬底上形成多晶硅栅极导体，并通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法来修整多晶硅部分。 修整步骤可以选择性地补偿n沟道和p沟道器件。 此外，修整膜可以任选地通过从各向异性和各向同性蚀刻中选择的方法去除。 此外，可以通过生长膜的各向异性蚀刻形成栅极导体间隔物。 所得到的晶体管可以包括栅极导体的经修剪的多晶硅部分，其中通过从选择性表面氧化和选择性表面氮化中选择的膜生长方法进行修整。

公开(公告)号：US06506653B1

公开(公告)日：2003-01-14

申请号：US09524677

申请日：2000-03-13

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/665

摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

摘要翻译： 提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。 此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。 这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。 以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。 优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。 沉积保形层并用掺杂剂注入。 执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

公开(公告)号：US06387783B1

公开(公告)日：2002-05-14

申请号：US09299267

申请日：1999-04-26

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L2128

CPC分类号： H01L29/42316 ,  H01L21/28581

摘要： Methods for forming a T-gate on a substrate are provided that employ a hybrid resist. The hybrid resist specifically is employed to define a base of the T-gate on the substrate with very high resolution. To define a base of the T-gate, a hybrid resist layer is deposited on the substrate. A mask having a reticle feature with an edge is provided and is positioned above the hybrid resist layer so that the edge of the reticle feature is above a desired location for the base of the T-gate. Thereafter, the hybrid resist layer is exposed to radiation through the mask, and the exposed hybrid resist layer is developed to define an opening therein for the base of the T-gate. Preferably the loop feature formed in the hybrid resist layer by the reticle feature during exposure is trimmed. The T-gate may be completed by employing any known T-gate fabrication techniques.

摘要翻译： 提供了在衬底上形成T形栅的方法，其采用混合抗蚀剂。 采用混合抗蚀剂专门用于以非常高的分辨率在衬底上限定T形栅极的基极。 为了限定T栅极的基极，在衬底上沉积混合抗蚀剂层。 提供了具有边缘的掩模版特征的掩模，并且位于混合抗蚀剂层之上，使得掩模版特征的边缘高于用于T形栅极的基底的期望位置。 此后，混合抗蚀剂层通过掩模暴露于辐射，并且暴露的混合抗蚀剂层被显影以在T形栅极的底部限定开口。 优选地，在曝光期间通过掩模版特征在混合抗蚀剂层中形成的环形特征被修整。 T栅极可以通过采用任何已知的T栅极制造技术来完成。