公开(公告)号：US07298175B1

公开(公告)日：2007-11-20

申请号：US11158579

申请日：2005-06-22

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H03K19/094

CPC分类号： H03K17/005 ,  H03K17/6257 ,  H03K17/693 ,  H03K2217/0036

摘要： An integrated circuit programmable multiplexer that reduces sub-threshold leakage current in deep sub-micron technology. The multiplexer uses a plurality of transistor stages, wherein each transistor of a subsequent stage is connected to at least two transistors of a prior stage, such that each transistor is in series with at least one other transistor. Transistors that are not part of the signal path through the multiplexer are deactivated, wherein a series of two or more deactivated transistors have significantly less sub-threshold leakage current than a single deactivated transistor. Configuration memory cells that store and communicate control signals to the multiplexer transistors are also connected to a low-voltage power supply when the multiplexer is not in use to reduce leakage current through the memory cells.

摘要翻译： 集成电路可编程多路复用器，可减少深亚微米技术中的亚阈值漏电流。 多路复用器使用多个晶体管级，其中后级的每个晶体管连接到前级的至少两个晶体管，使得每个晶体管与至少一个其它晶体管串联。 不是通过多路复用器的信号路径的一部分的晶体管被​​去激活，其中一系列两个或更多个去激活晶体管具有比单个去激活晶体管明显更少的次阈值漏电流。 当多路复用器不用于减少通过存储器单元的泄漏电流时，存储和传送控制信号到多路复用器晶体管的配置存储单元也连接到低压电源。

公开(公告)号：US07218168B1

公开(公告)日：2007-05-15

申请号：US11210497

申请日：2005-08-24

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G05F1/10

CPC分类号： G05F1/56

摘要： A voltage regulator and a method for voltage regulation are described. An adjustable driver is coupled to receive an input voltage, a gating voltage, and first control signaling. The adjustable driver includes driver transistors. The adjustable driver is configured to provide a drive current responsive to the gating voltage. The drive current is provided through one or more of the driver transistors at least a portion of which are selectively gated responsive to the first control signaling. A controller is coupled to receive the input voltage and the gating voltage. The controller is configured to provide the first control signaling responsive to the gating voltage. Control circuitry is configured to provide the gating voltage responsive to load current.

摘要翻译： 描述了电压调节器和电压调节方法。 耦合可调节驱动器以接收输入电压，门控电压和第一控制信号。 可调驱动器包括驱动晶体管。 可调节驱动器被配置为提供响应于门控电压的驱动电流。 通过一个或多个驱动器晶体管提供驱动电流，其中至少一部分响应于第一控制信号而选择性选通。 控制器被耦合以接收输入电压和门控电压。 控制器被配置为响应于门控电压提供第一控制信号。 控制电路被配置为响应于负载电流提供门控电压。

公开(公告)号：US06788101B1

公开(公告)日：2004-09-07

申请号：US10366956

申请日：2003-02-13

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H03K19003

CPC分类号： H04L25/0276 ,  H03K19/017581 ,  H04L25/028 ,  H04L25/0292

摘要： A programmable interface circuit is disclosed, in accordance with one embodiment, which supports differential and single-ended signaling. For example, an input buffer within the programmable interface circuit is configurable to receive differential signals or single-ended signals. A multiplexer provides the appropriate reference signal to the input buffer, when configured to receive single-ended signals, by selecting the reference signal from a plurality of reference buses. The multiplexer, along with a capacitor, may also provide lowpass filtering of the reference signal. Furthermore, an output buffer may be configurable utilizing techniques similar to that described for the input buffer.

公开(公告)号：US08941233B1

公开(公告)日：2015-01-27

申请号：US13402632

申请日：2012-02-22

申请人： Tony Ngai ,  Arifur Rahman

发明人： Tony Ngai ,  Arifur Rahman

IPC分类号： H01L23/34

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/15311

摘要： Integrated circuit (IC) packages with an inter-die thermal spreader are disclosed. A disclosed IC package includes a plurality of stacked dies disposed on a package substrate. A heat spreader is disposed on a top die of the plurality of stacked dies. The IC package further includes a thermal spreader layer disposed adjacent to at least one die of the plurality of stacked dies. The thermal spreader layer may extend out of a periphery of the plurality of stacked dies and may be attached to the heat spreader through a support member.

摘要翻译： 公开了具有管芯间散热器的集成电路（IC）封装。 所公开的IC封装包括设置在封装基板上的多个堆叠管芯。 散热器设置在多个堆叠的模具的顶模上。 IC封装还包括与多个堆叠管芯的至少一个管芯相邻设置的散热器层。 散热器层可以延伸出多个堆叠的模具的周边，并且可以通过支撑构件附接到散热器。

公开(公告)号：US08791573B1

公开(公告)日：2014-07-29

申请号：US13601894

申请日：2012-08-31

申请人： Hui Liu ,  Christopher F. Lane ,  Arifur Rahman ,  Jianming Huang

发明人： Hui Liu ,  Christopher F. Lane ,  Arifur Rahman ,  Jianming Huang

IPC分类号： H01L23/48 ,  G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/5286 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： Techniques and mechanisms for providing embedded Input/Output (IO) blocks in a floor plan of a semiconductor device are provided, where the embedded IO blocks constitute partial columns (i.e., they do not extend from the bottom through to the top of the semiconductor device). In some embodiments, the partial column IO banks are skewed away from one another. In some embodiments, the partial column IO banks are located away from the center of the semiconductor device. Techniques and mechanisms for implementing symmetrical package routing using skewed partial column IO banks are also provided.

摘要翻译： 提供了在半导体器件的平面图中提供嵌入式输入/输出（IO）块的技术和机制，其中嵌入式IO块构成部分列（即，它们不从半导体器件的底部到顶部延伸） ）。 在一些实施例中，部分列IO组彼此偏斜。 在一些实施例中，部分列IO组位于远离半导体器件的中心的位置。 还提供了使用偏斜部分列IO库来实现对称封装路由的技术和机制。

公开(公告)号：US08779553B2

公开(公告)日：2014-07-15

申请号：US13162541

申请日：2011-06-16

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H01L29/06

CPC分类号： H01L25/0652 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

摘要： A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC.

摘要翻译： 涉及具有插入器的集成电路（IC）的电路设计的方法可以包括识别在内插器的区域内实现的有效资源，其暴露于超过内插器上的归一化应力量的应力量并选择性地分配 根据在IC内实现的电路设计的应力感知分析，将要在IC内实现的有源电源的电路设计的元件。

公开(公告)号：US20130069247A1

公开(公告)日：2013-03-21

申请号：US13235166

申请日：2011-09-16

申请人： Arifur Rahman ,  Jon M. Long ,  Yuanlin Xie

发明人： Arifur Rahman ,  Jon M. Long ,  Yuanlin Xie

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L25/0652 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H05K1/141 ,  H05K3/4697 ,  H05K2201/1053 ,  H01L2924/014 ,  H01L2924/00

摘要： An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.

摘要翻译： 一种装置包括基板和包括电子电路的一对管芯。 基板包括空腔。 模具中的一个设置在形成在基板中的空腔中。 另一个管芯设置在第一管芯上方并且电耦合到第一管芯。

公开(公告)号：US08384225B2

公开(公告)日：2013-02-26

申请号：US12945700

申请日：2010-11-12

申请人： Arifur Rahman ,  Bahareh Banijamali

发明人： Arifur Rahman ,  Bahareh Banijamali

IPC分类号： H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/486 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor device includes a substrate having a top surface and a bottom surface, and a through-silicon via (TSV) extending from the top surface of the substrate to the bottom surface of the substrate, the TSV having a height and a side profile extending along a longitudinal axis, wherein the side profile has an upper segment forming a first angle relative to the longitudinal axis, and a lower segment forming a second angle relative to the longitudinal axis, the second angle being different from the first angle, and wherein the lower segment has a height that is less than 20% of the height of the TSV.

摘要翻译： 半导体器件包括具有顶表面和底表面的衬底以及从衬底的顶表面延伸到衬底的底表面的穿硅通孔（TSV），TSV具有高度和侧面延伸 沿着纵向轴线，其中所述侧部轮廓具有相对于所述纵向轴线形成第一角度的上部部分，以及相对于所述纵向轴线形成第二角度的下部部分，所述第二角度与所述第一角度不同，并且其中 下段高度小于TSV高度的20％。

公开(公告)号：US20120331435A1

公开(公告)日：2012-12-27

申请号：US13170020

申请日：2011-06-27

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G06F17/50

CPC分类号： H01L25/0655 ,  H01L23/147 ,  H01L23/481 ,  H01L23/5384 ,  H01L25/0652 ,  H01L25/072 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06572 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/00012

摘要： A method of integrated circuit design using through silicon vias (TSVs) can include determining that a stress field to which a first active circuit element of a circuit block is exposed and a stress field to which a second active circuit element of the circuit block is exposed are mismatched. Mismatch between the stress field of the first active circuit element and the stress field of the second active circuit element can be reduced by modifying a layout of the die for a TSV.

摘要翻译： 使用硅通孔（TSV）的集成电路设计的方法可以包括确定暴露电路块的第一有源电路元件的应力场和电路块的第二有源电路元件所暴露的应力场 不匹配。 可以通过修改TSV的管芯的布局来减小第一有源电路元件的应力场与第二有源电路元件的应力场之间的不匹配。

公开(公告)号：US08299590B2

公开(公告)日：2012-10-30

申请号：US12043115

申请日：2008-03-05

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H01L23/02

CPC分类号： H01L25/0652 ,  H01L23/3128 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104

摘要： Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device includes a primary integrated circuit (IC) die and at least one secondary IC die mounted on the primary IC die. A heat extraction element includes a base mounted to the semiconductor device such that each of the at least one secondary IC die is between the primary IC die and the heat extraction element. At least one dummy fill is adjacent the at least one secondary IC die, and each thermally couples the primary IC die to the heat extraction element.

摘要翻译： 描述了具有降低的热扩散电阻的半导体组件及其制造方法。 在一个示例中，半导体器件包括主集成电路（IC）裸片和安装在主IC芯片上的至少一个次级IC芯片。 散热元件包括安装到半导体器件的基座，使得至少一个次级IC芯片中的每一个都位于主IC芯片和热提取元件之间。 至少一个虚拟填充物与至少一个次级IC芯片相邻，并且每个模拟填充物将初级IC管芯热耦合到热提取元件。