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公开(公告)号：US09250286B2
公开(公告)日：2016-02-02
申请号：US14246529
申请日：2014-04-07
Inventor： An-Chun Tu , Chen-Ming Huang , Chih-Jen Wu , Chin-Hsiang Lin
CPC classification number: G01R31/2644 , G01R31/2884 , H01L22/14 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes.
Abstract translation: 一种使用电阻器件执行的方法，其中所述电阻器件包括具有通过栅电极的最长尺寸的电介质和电触点与栅电极分离的有源区的衬底，所述方法包括执行一个或多个工艺以形成 电阻器件，测量电触点之间的电阻，并将所测量的电阻与一个或多个过程中的变化相关联。
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公开(公告)号：US20150303106A1
公开(公告)日：2015-10-22
申请号：US14752402
申请日：2015-06-26
Inventor： Sung-Li Wang , Ding-Kang Shih , Chin-Hsiang Lin , Sey-Ping Sun , Clement Hsingjen Wann
IPC: H01L21/768 , H01L29/66 , H01L29/417
CPC classification number: H01L21/76856 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/285 , H01L21/76802 , H01L21/76831 , H01L21/76843 , H01L21/76888 , H01L23/485 , H01L29/0684 , H01L29/41783 , H01L29/41791 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/7851 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.
Abstract translation: 本发明涉及半导体器件的接触结构。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的沟槽; 填充沟槽的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在所述应变材料上具有开口的层间介电层（ILD）层，其中所述开口包括电介质侧壁和应变材料底部; 涂覆所述开口的侧壁和底部的电介质层，其中所述电介质层具有1nm至10nm的厚度; 以及填充介电层的涂覆开口的金属层。
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公开(公告)号：US20150192616A1
公开(公告)日：2015-07-09
申请号：US14659268
申请日：2015-03-16
Inventor： Jui-Long Chen , Chien-Chih Liao , Chin-Hsiang Lin , Hui-yun Chao , Jong-I Mou , Tseng Chin Lo , Ta-Yung Lee
CPC classification number: G01R1/07364 , G01R1/06705 , G01R31/2887 , G01R31/2891 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/00 , H01L2924/0002
Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.
Abstract translation: 公开了一种用于将诸如晶片级测试探针的探针与晶片接触件对准的系统和方法。 一种示例性方法包括在晶片测试系统处接收包含多个对准触点的晶片和包含多个探针点的探针卡。 接收到历史偏移校正。 基于历史偏移校正，确定探针卡相对于晶片的取向值。 使用取向值将探针卡与晶片对准，以试图使第一探针点与第一对准触点接触。 评估第一探针点和第一对准接触点的连接性。 使用对准的探针卡进行晶片的电气测试，并且基于取向值更新历史偏移校正。
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公开(公告)号：US20150041918A1
公开(公告)日：2015-02-12
申请号：US13963887
申请日：2013-08-09
Inventor： Clement Hsingjen Wann , Sey-Ping Sun , Ling-Yen Yeh , Chi-Yuan Shih , Li-Chi Yu , Chun Hsiung Tsai , Chin-Hsiang Lin , Neng-Kuo Chen , Meng-Chun Chang , Ta-Chun Ma , Gin-Chen Huang , Yen-Chun Huang
CPC classification number: H01L21/28518 , H01L27/0886 , H01L29/0649 , H01L29/161 , H01L29/41791 , H01L29/45 , H01L29/66545 , H01L29/66795 , H01L29/785
Abstract: A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals.
Abstract translation: 一种方法包括在晶片的主表面上生长外延半导体区域。 外延半导体区域具有朝上的面向上的朝向小面和朝下的向下的小面。 该方法还包括形成与向上朝向的小面接触的第一金属硅化物层，以及形成接触向下的小面的第二金属硅化物层。 第一金属硅化物层和第二金属硅化物层包括不同的金属。
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公开(公告)号：US20140363943A1
公开(公告)日：2014-12-11
申请号：US14469394
申请日：2014-08-26
Inventor： Sung-Li Wang , Ding-Kang Shih , Chin-Hsiang Lin , Sey-Ping Sun , Clement Hsingjen Wann
IPC: H01L29/66 , H01L29/78 , H01L29/417 , H01L29/06
CPC classification number: H01L29/66636 , H01L21/02164 , H01L21/02172 , H01L21/02178 , H01L21/02186 , H01L21/02255 , H01L21/02532 , H01L21/02579 , H01L21/02614 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/30604 , H01L21/76224 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L29/0642 , H01L29/0847 , H01L29/41758 , H01L29/41791 , H01L29/45 , H01L29/66477 , H01L29/66545 , H01L29/66628 , H01L29/66795 , H01L29/7378 , H01L29/78 , H01L29/7848 , H01L29/785 , H01L2924/0002 , H01L2924/00
Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.
Abstract translation: 本发明涉及半导体器件的接触结构。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的沟槽; 填充沟槽的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在所述应变材料上具有开口的层间介电层（ILD）层，其中所述开口包括电介质侧壁和应变材料底部; 在开口的侧壁和底部上的半导体层; 半导体层上的介电层; 以及填充介电层的开口的金属层。
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Patent Agency Ranking
公开(公告)号：US20140159243A1
公开(公告)日：2014-06-12
申请号：US14182912
申请日：2014-02-18
Inventor： Soon-Kang Huang , Han-Hsin Kuo , Chi-Ming Yang , Shwang-Ming Jeng , Chin-Hsiang Lin
IPC: H01L23/538 , H01L21/67
CPC classification number: H01L23/5386 , H01L21/02074 , H01L21/28079 , H01L21/67011 , H01L21/7684 , H01L29/495 , H01L29/78 , H01L2924/0002 , H01L2924/00
Abstract: The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.
Abstract translation: 本公开提供了一种制造半导体器件的方法，通过这种方法制造的半导体器件和用于执行这种方法的化学机械抛光（CMP）工具。 在一个实施例中，制造半导体器件的方法包括在衬底上的电介质层的沟槽中提供包括金属导体的集成电路（IC）晶片，以及执行化学机械抛光（CMP）工艺以平坦化金属导体 和电介质层。 该方法还包括清洁平坦化的金属导体和电介质层以除去CMP工艺中的残留物，用醇漂洗清洁的金属导体和介电层，并在惰性气体环境中干燥漂洗的金属导体和电介质层。
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67.发明申请公开(公告)号：US20130286371A1
公开(公告)日：2013-10-31
申请号：US13923968
申请日：2013-06-21
Inventor： George Liu , Kuei Shun Chen , Norman Chen , Vencent Chang , Chin-Hsiang Lin
IPC: G03F7/20
CPC classification number: G03F7/70058 , G03F7/70125 , G03F7/70425
Abstract: System and method for enhancing optical lithography methodology for hole patterning in semiconductor fabrication are described. In one embodiment, a photolithography system comprises an illumination system for conditioning light from a light source, the illumination system producing a three-pore illumination pattern; a reticle comprising at least a portion of a pattern to be imaged onto a substrate, wherein the three-pore illumination pattern produced by the illumination system is projected through the reticle; and a projection lens disposed between the reticle and the substrate.
Abstract translation: 描述了用于增强半导体制造中的孔图案化的光学光刻方法的系统和方法。 在一个实施例中，光刻系统包括用于调节来自光源的光的照明系统，所述照明系统产生三孔照明图案; 包括至少一部分要成像到基底上的图案的掩模版，其中由照明系统产生的三孔照明图案通过掩模版投射; 以及设置在掩模版和基板之间的投影透镜。
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公开(公告)号：US12266539B2
公开(公告)日：2025-04-01
申请号：US18225623
申请日：2023-07-24
Inventor： Ru-Gun Liu , Chih-Ming Lai , Wei-Liang Lin , Yung-Sung Yen , Ken-Hsien Hsieh , Chin-Hsiang Lin
IPC: H01L21/311 , H01L21/027 , H01L21/768
Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
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公开(公告)号：US12249507B2
公开(公告)日：2025-03-11
申请号：US17885114
申请日：2022-08-10
Inventor： An-Ren Zi , Ching-Yu Chang , Chin-Hsiang Lin
IPC: H01L21/027 , H01L21/67
Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.
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70.发明授权公开(公告)号：US12235589B2
公开(公告)日：2025-02-25
申请号：US18206970
申请日：2023-06-07
Inventor： Shinn-Sheng Yu , Ru-Gun Liu , Hsu-Ting Huang , Kenji Yamazoe , Minfeng Chen , Shuo-Yen Chou , Chin-Hsiang Lin
Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.
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