公开(公告)号：US11063213B2

公开(公告)日：2021-07-13

申请号：US16664815

申请日：2019-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  David Dai ,  Chung-Ju Lee

IPC: H01L47/00 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L27/24 ,  H01L43/08

Abstract: A method includes depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer; etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element; depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; and etching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer.

公开(公告)号：US10700264B2

公开(公告)日：2020-06-30

申请号：US16511862

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.

公开(公告)号：US20200098978A1

公开(公告)日：2020-03-26

申请号：US16510296

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.

公开(公告)号：US10461246B2

公开(公告)日：2019-10-29

申请号：US15706709

申请日：2017-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  David Dai ,  Chung-Ju Lee

IPC: H01L47/00 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L27/24 ,  H01L43/08

Abstract: A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.

公开(公告)号：US10355198B2

公开(公告)日：2019-07-16

申请号：US15811405

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A memory device includes an MTJ structure and a first metal residue. The MTJ structure includes a top surface having a first width, a bottom surface having a second width greater than the first width, and a stepped sidewall structure between the top surface and the bottom surface. The stepped sidewall structure includes a first sidewall, a second sidewall, and an intermediary surface connecting the first sidewall to the second sidewall. The first metal residue is in contact with the first sidewall and not in contact with the second sidewall.

公开(公告)号：US10270028B1

公开(公告)日：2019-04-23

申请号：US15813055

申请日：2017-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Chih-Wei Lu ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22

Abstract: A method for manufacturing a memory device, the method includes forming an opening in a dielectric layer; overfilling the opening with a bottom electrode layer; removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode; and forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.

公开(公告)号：US20180301416A1

公开(公告)日：2018-10-18

申请号：US16017039

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L23/528 ,  H01L23/538 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure, in some embodiments, relates to an interconnect structure. The interconnect structure has a metal body disposed over a substrate, and a metal projection protruding outward from an upper surface of the metal body. A dielectric layer is disposed over the substrate and surrounds the metal body and the metal projection. A barrier layer separates the metal body and the metal projection from the dielectric layer.

公开(公告)号：US09799558B2

公开(公告)日：2017-10-24

申请号：US14942386

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Carlos H. Diaz ,  Chung-Ju Lee ,  Shau-Lin Shue ,  Tien-I Bao

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/288 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7688 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53228 ,  H01L2221/1063

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a first dielectric layer over a substrate and forming a sacrificial layer over the first dielectric layer. The method further includes forming an opening in the sacrificial layer and etching the first dielectric layer to form a via hole through the opening. The method further includes forming a conductive structure in the via hole and the opening and removing the sacrificial layer to expose an upper portion of the conductive structure. The method further includes forming a second dielectric layer around the upper portion of the conductive material.

公开(公告)号：US09786549B2

公开(公告)日：2017-10-10

申请号：US15083484

申请日：2016-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sunil Kumar Singh ,  Chung-Ju Lee ,  Tien-I Bao

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76808 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2221/1031 ,  H01L2221/1036 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

公开(公告)号：US09633949B2

公开(公告)日：2017-04-25

申请号：US15153967

申请日：2016-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L29/06 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body. The integrated circuit also has a projection disposed over the conductive body. The projection has tapered sidewalls that cause a lower surface of the projection to have a greater width than an upper surface of the projection and a smaller width than an upper surface of the conductive body. A dielectric material surrounds the conductive body and the projection.