公开(公告)号：US20210050220A1

公开(公告)日：2021-02-18

申请号：US17070461

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang ,  Yao-Wen Chang

IPC: H01L21/311 ,  H01L45/00 ,  H01L21/3105 ,  H01L43/02 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.

公开(公告)号：US20210043443A1

公开(公告)日：2021-02-11

申请号：US16534310

申请日：2019-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-He Chou ,  Sheng-Chau Chen ,  Ming-Tung Wu ,  Hsun-Chung Kuang

IPC: H01L21/02 ,  B08B5/02 ,  B08B3/10 ,  H01L21/67 ,  H01L21/687

Abstract: In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.

公开(公告)号：US10727097B2

公开(公告)日：2020-07-28

申请号：US14710227

申请日：2015-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sheng-Chau Chen ,  Chih-Hui Huang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Xiao-Meng Chen

IPC: H01L21/67 ,  H01L21/18 ,  H01L33/00 ,  H01L21/02 ,  H01L21/687

Abstract: The mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. The mechanisms for a hybrid bonding and a integrated system are also provided.

公开(公告)号：US20180158728A1

公开(公告)日：2018-06-07

申请号：US15423771

申请日：2017-02-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Chang Chu ,  Yao-Wen Chang ,  Sheng-Chau Chen ,  Alexander KALNITSKY

IPC: H01L21/768 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675

Abstract: A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric structure has an opening. The tungsten plug is embedded in the opening of the dielectric structure. The bottom electrode extends along top surfaces of the dielectric structure and the tungsten plug. The resistance switching element is present over the bottom electrode. The top electrode is present over the resistance switching element.

公开(公告)号：US20170358620A1

公开(公告)日：2017-12-14

申请号：US15180395

申请日：2016-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Sheng-Chan Li ,  Zhi-Yang Wang

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor having a passivation layer is provided. The CMOS image sensor includes a sensing device substrate. Isolation structures are positioned within trenches of the sensing device substrate. The isolation structures are arranged along opposing sides of a plurality of image sensing devices. The CMOS image sensor also includes a passivation layer. The passivation layer includes passivation sidewalls arranged along the sidewalls of the isolation structures. A metallic grid overlies the passivation layer. The metallic grid includes a metal framework surrounding openings overlying the plurality of image sensing devices. The passivation layer further includes passivation section underlying the openings.

公开(公告)号：US09281331B2

公开(公告)日：2016-03-08

申请号：US14308910

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Chih-Yu Lai ,  Kuo-Ming Wu ,  Kuo-Hwa Tzeng ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L31/062 ,  H01L27/146 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/14614 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66621

Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.

Abstract translation: 提供了一种有源像素传感器（APS）的垂直栅极传输晶体管。 晶体管包括半导体衬底，延伸到半导体衬底中的垂直沟槽，垂直沟槽的电介质衬里，以及填充衬里垂直沟槽的垂直栅极。 电介质包括超过3.9的介电常数（即二氧化硅的介电常数）。 还提供了制造垂直栅极转移晶体管的方法，包括垂直栅极转移晶体管的APS，制造APS的方法以及包括多个APS的图像传感器。

公开(公告)号：US20150372034A1

公开(公告)日：2015-12-24

申请号：US14308910

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Chih-Yu Lai ,  Kuo-Ming Wu ,  Kuo-Hwa Tzeng ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L27/146 ,  H01L29/423 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L27/14614 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66621

Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.

Abstract translation: 提供了一种有源像素传感器（APS）的垂直栅极传输晶体管。 晶体管包括半导体衬底，延伸到半导体衬底中的垂直沟槽，垂直沟槽的电介质衬里，以及填充衬里垂直沟槽的垂直栅极。 电介质包括超过3.9的介电常数（即二氧化硅的介电常数）。 还提供了制造垂直栅极转移晶体管的方法，包括垂直栅极转移晶体管的APS，制造APS的方法以及包括多个APS的图像传感器。