公开(公告)号：US11980016B2

公开(公告)日：2024-05-07

申请号：US17813782

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US11728432B2

公开(公告)日：2023-08-15

申请号：US17352587

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76224

Abstract: A semiconductor device comprises a memory macro including a well pick-up (WPU) area oriented lengthwise along a first direction, and memory bit areas adjacent to the WPU area. In the WPU area, the memory macro includes n-type and p-type wells arranged alternately along the first direction with well boundaries between adjacent wells; gate structures over the wells and oriented lengthwise along the first direction; a first dielectric layer disposed at each of the well boundaries; first contact features disposed over one of the p-type wells; and second contact features disposed over one of the n-type wells. From a top view, the first dielectric layer extends along a second direction perpendicular to the first direction and separates all the gate structures in the first WPU area, the first contact features are disposed between the gate structures, and the second contact features are disposed between the gate structures.

公开(公告)号：US11728405B2

公开(公告)日：2023-08-15

申请号：US16820175

申请日：2020-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L29/165

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76832 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor structure includes source/drain (S/D) features disposed over a semiconductor substrate, a metal gate stack disposed between the S/D features, where the metal gate stack traverses a channel region between the S/D features, gate spacers disposed on sidewalls of the metal gate stack, and an etch-stop layer (ESL) disposed over the gate spacers and the S/D features. The semiconductor structure further includes an oxide liner disposed on the ESL, where the oxide liner includes silicon oxide and silicon dioxide, and an interlayer dielectric (ILD) layer disposed on the oxide liner, where composition of the ILD layer is different from composition of the oxide liner.

公开(公告)号：US11527380B2

公开(公告)日：2022-12-13

申请号：US16837724

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Chieh Meng ,  Chui-Ya Peng ,  Shih-Hao Lin

IPC: H01J37/32 ,  H01J37/317 ,  H01J37/08 ,  H01L21/265

Abstract: An ion implantation system including an ion implanter, a dopant source gas supply system and a monitoring system is provided. The ion implanter is inside a housing and includes an ion source unit. The dopant source gas supply system includes a first and a second dopant source gas storage cylinder in a gas cabinet outside of the housing and configured to supply a dopant source gas to the ion source unit, and a first and a second dopant source gas supply pipe coupled to respective first and second dopant source gas storage cylinders. Each of the first and second dopant source gas supply pipes includes an inner pipe and an outer pipe enclosing the inner pipe. The monitoring system is coupled to the outer pipe of each of the first and the second dopant source gas supply pipes.

公开(公告)号：US20220384454A1

公开(公告)日：2022-12-01

申请号：US17884442

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/11

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US20220277789A1

公开(公告)日：2022-09-01

申请号：US17749325

申请日：2022-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Pao ,  Shih-Hao Lin ,  Kian-Long Lim

IPC: G11C11/418 ,  G11C11/419

Abstract: Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver.

公开(公告)号：US11430788B2

公开(公告)日：2022-08-30

申请号：US16798685

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Yi Lin ,  Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.

公开(公告)号：US11348929B2

公开(公告)日：2022-05-31

申请号：US17035298

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Chia-En Huang ,  Shih-Hao Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11521 ,  H01L23/522 ,  H01L27/11568 ,  G11C7/18 ,  H01L29/872 ,  G11C8/14

Abstract: A memory device includes a substrate, a first gate structure and a second gate structure, first, second, third source/drain structures, gate spacers, a first via and a second via, and a semiconductor layer. The first gate structure and the second gate structure are over the substrate. The first, second, third source/drain structures are over the substrate, in which the first and second source/drain structures are on opposite sides of the first gate structure, the second and third source/drain structures are on opposite sides of the second gate structure. The gate spacers are on opposite sidewalls of the first and second gate structures. The first via and the second via are over the first gate structure and the second gate structure, respectively, in which the first via is in contact with the first gate structure. The semiconductor layer is between the second via and the second gate structure.

公开(公告)号：US11296095B2

公开(公告)日：2022-04-05

申请号：US16900200

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Shih-Hao Lin ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L27/112 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/786

Abstract: A memory device includes a substrate, first semiconductor layers and second semiconductor layers alternately stacked over the substrate, a first gate structure and a second gate structure crossing the first semiconductor layers and the second semiconductor layers, a first via and a second via over the first gate structure and the second gate structure, and a first word line and a second word line over the first via and the second via. Along a lengthwise direction of the first and second gate structures, a width of the first semiconductor layers is narrower than a width of the second semiconductor layers.

公开(公告)号：US11264393B2

公开(公告)日：2022-03-01

申请号：US16776205

申请日：2020-01-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Lin Chen ,  Chao-Yuan Chang ,  Ping-Wei Wang ,  Fu-Kai Yang ,  Ting Fang ,  I-Wen Wu ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L29/417 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L29/40

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.