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    INTERCONNECT STRUCTURE WITH AIR-GAPS
    62.
    发明申请
    INTERCONNECT STRUCTURE WITH AIR-GAPS 有权

    公开(公告)号：US20210159175A1

    公开(公告)日：2021-05-27

    申请号：US17144592

    申请日：2021-01-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire arranged within an inter-level dielectric (ILD) layer and a second interconnect wire arranged within the ILD layer. A dielectric material continuously extends over the first interconnect wire and the ILD layer. The dielectric material is further disposed between sidewalls of the first interconnect wire and one or more air-gaps arranged along opposing sides of the first interconnect wire. A via is disposed over the second interconnect wire and extends through the dielectric material. A second ILD layer is disposed on the dielectric material and surrounds the via.

    Hybrid copper structure for advance interconnect usage
    63.
    发明授权
    Hybrid copper structure for advance interconnect usage 有权

    公开(公告)号：US10290580B2

    公开(公告)日：2019-05-14

    申请号：US15819280

    申请日：2017-11-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsiang-Wei Liu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Tien-Lu Lin

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: The present disclosure, in some embodiments, relates to an integrated chip having a back-end-of-the-line interconnect stack. The integrated chip has a dielectric structure arranged over a substrate. A first interconnect structure is arranged within the dielectric structure and has sidewalls and a horizontally extending surface that define a recess within a lower surface of the first interconnect structure facing the substrate. A lower interconnect structure is arranged within the dielectric structure and extends from within the recess to a location between the first interconnect structure and the substrate. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials.

    Structure and formation method of semiconductor device structure
    64.
    发明授权
    Structure and formation method of semiconductor device structure 有权

    公开(公告)号：US10103102B2

    公开(公告)日：2018-10-16

    申请号：US15855795

    申请日：2017-12-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jian-Hua Chen ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Chia-Tien Wu ,  Tien-Lu Lin ,  Tien-I Bao

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer over a semiconductor substrate. The semiconductor device structure also includes a first conductive feature in the dielectric layer. A portion of the dielectric layer has a top surface that is provided on a different level in relation to a top surface of the first conductive feature. The semiconductor device structure further includes a second conductive feature in the dielectric layer and extending from a bottom surface of the first conductive feature. The portion of the dielectric layer is separated from the second conductive feature by a gap. A distance between the portion of the dielectric layer and the second conductive feature becomes smaller along a direction from the top surface of the first conductive feature towards the bottom surface of the first conductive feature.

    SOURCE/DRAIN ISOLATION STRUCTURE AND METHODS THEREOF
    70.
    发明申请
    SOURCE/DRAIN ISOLATION STRUCTURE AND METHODS THEREOF 有权

    公开(公告)号：US20240379408A1

    公开(公告)日：2024-11-14

    申请号：US18783905

    申请日：2024-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

    IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

    Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

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