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    Bottom-up Formation of Contact Plugs
    61.
    发明申请
    Bottom-up Formation of Contact Plugs 有权

    公开(公告)号：US20220359285A1

    公开(公告)日：2022-11-10

    申请号：US17814737

    申请日：2022-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

    IPC: H01L21/768 ,  H01L21/225 ,  H01L29/40 ,  H01L29/417

    Abstract: A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

    Metrology method in wafer transportation
    62.
    发明授权
    Metrology method in wafer transportation 有权

    公开(公告)号：US11387123B2

    公开(公告)日：2022-07-12

    申请号：US16857446

    申请日：2020-04-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Powen Huang ,  Yao-Yuan Shang ,  Kuo-Shu Tseng ,  Yen-Yu Chen ,  Chun-Chih Lin ,  Yi-Ming Dai

    IPC: G05B19/418 ,  H01L21/67 ,  H01L21/677 ,  H01L21/673 ,  H01L21/02 ,  G01D7/00 ,  G01D5/00 ,  B08B3/04

    Abstract: A method for fault detection in a fabrication facility is provided. The method includes moving a wafer carrier along a predetermined path multiple times using a transportation apparatus. The method also includes collecting data associated with an environmental condition within the wafer carrier or around the wafer carrier using a metrology tool on the predetermined path in a previous movement of the transportation apparatus. The method further includes measuring the environmental condition within the wafer carrier or around the wafer carrier using the metrology tool during the movement of the wafer carrier. In addition, the method includes issuing a warning when the measured environmental condition is outside a range of acceptable values. The range of acceptable values is derived from the data collected in the previous movement of the transportation apparatus.

    IMAGE SENSOR WITH OVERLAP OF BACKSIDE TRENCH ISOLATION STRUCTURE AND VERTICAL TRANSFER GATE
    63.
    发明申请
    IMAGE SENSOR WITH OVERLAP OF BACKSIDE TRENCH ISOLATION STRUCTURE AND VERTICAL TRANSFER GATE 有权

    公开(公告)号：US20210210532A1

    公开(公告)日：2021-07-08

    申请号：US16733433

    申请日：2020-01-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Feng-Chi Hung ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wei Chuang Wu ,  Yen-Yu Chen ,  Chih-Kuan Yu

    IPC: H01L27/146

    Abstract: Some embodiments are directed towards an image sensor device. A photodetector is disposed in a semiconductor substrate, and a transfer transistor is disposed over photodetector. The transfer transistor includes a transfer gate having a lateral portion extending over a frontside of the semiconductor substrate and a vertical portion extending to a first depth below the frontside of the semiconductor substrate. A gate dielectric separates the lateral portion and the vertical portion from the semiconductor substrate. A backside trench isolation structure extends from a backside of the semiconductor substrate to a second depth below the frontside of the semiconductor substrate. The backside trench isolation structure laterally surrounds the photodetector, and the second depth is less than the first depth such that a lowermost portion of the vertical portion of the transfer transistor has a vertical overlap with an uppermost portion of the backside trench isolation structure.

    Threshold voltage tuning for fin-based integrated circuit device
    65.
    发明授权
    Threshold voltage tuning for fin-based integrated circuit device 有权

    公开(公告)号：US10790196B2

    公开(公告)日：2020-09-29

    申请号：US15808285

    申请日：2017-11-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

    IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/088 ,  H01L27/12

    Abstract: Methods for tuning threshold voltages of fin-like field effect transistor devices are disclosed herein. An exemplary method includes forming a first opening in a first gate structure and a second opening in a second gate structure. The first gate structure is disposed over a first fin structure, and the second gate structure is disposed over a second fin structure. The method further includes filling the first opening and the second opening by forming a gate dielectric layer, forming a threshold voltage tuning layer over the gate dielectric layer, etching back the threshold voltage tuning layer in the second opening, forming a work function layer over the threshold voltage tuning layer, and forming a metal fill layer over the work function layer. The threshold voltage tuning layer includes tantalum and nitrogen. The etching back uses a tungsten-chloride containing precursor.

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