公开(公告)号：US11061318B2

公开(公告)日：2021-07-13

申请号：US16748551

申请日：2020-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hsiang Lo ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC: G06F111/06 ,  G06F111/10 ,  G03F1/36 ,  G03F1/70 ,  H01L21/027 ,  G03F7/20

Abstract: Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.

公开(公告)号：US11004729B2

公开(公告)日：2021-05-11

申请号：US16374150

申请日：2019-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun Liu ,  Chin-Hsiang Lin ,  Chih-Ming Lai ,  Wei-Liang Lin ,  Yung-Sung Yen

IPC: H01L27/12 ,  H01L21/768

Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

公开(公告)号：US20210134657A1

公开(公告)日：2021-05-06

申请号：US17120989

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Nien Su ,  Shu-Huei Suen ,  Jyu-Horng Shieh ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/263

Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

公开(公告)号：US10971363B2

公开(公告)日：2021-04-06

申请号：US16669065

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Lai ,  Shih-Ming Chang ,  Wei-Liang Lin ,  Chin-Yuan Tseng ,  Ru-Gun Liu

IPC: H01L21/311 ,  H01L21/033

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure.

公开(公告)号：US10962892B2

公开(公告)日：2021-03-30

申请号：US16227939

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Jie Lee ,  Shih-Chun Huang ,  Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Yung-Sung Yen ,  Ru-Gun Liu

IPC: G03F9/00 ,  G03F7/20

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

公开(公告)号：US10962875B2

公开(公告)日：2021-03-30

申请号：US16700336

申请日：2019-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Ting Huang ,  Chih-Shiang Chou ,  Ru-Gun Liu

IPC: G03F1/36 ,  G03F1/80 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/26 ,  G03F1/78 ,  H01L21/027 ,  H01L21/66 ,  G06F30/20 ,  G06F30/398 ,  G06F119/18

Abstract: An integrated circuit (IC) method is provided. The method includes building a mask model to simulate an aerial mask image of a mask, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask; calibrating the CLC model using measured wafer data and the calibrated mask model; performing an optical proximity correction (OPC) process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication. Alternatively, the method includes measuring a mask image of a mask optically projected on a wafer with an instrument; calibrating a mask model using the measured mask image; calibrating a CLC model using measured wafer data and the calibrated mask model; and performing an OPC process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication.

公开(公告)号：US10916475B2

公开(公告)日：2021-02-09

申请号：US16206803

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jui-Yao Lai ,  Ying-Yan Chen ,  Yen-Ming Chen ,  Sai-Hooi Yeong ,  Yung-Sung Yen ,  Ru-Gun Liu

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417 ,  H01L23/535

Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.

公开(公告)号：US10860774B2

公开(公告)日：2020-12-08

申请号：US16059367

申请日：2018-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F30/398 ,  G03F1/36

Abstract: The present disclosure relates to a method of data preparation. The method, in some embodiments, performs a first data preparation process using a data preparation element. The first data preparation process modifies a plurality of shapes of an integrated chip (IC) design that comprises a graphical representation of a layout used to fabricate an integrated chip. A plurality of additional shapes are added to the IC design using an additional shape insertion element. The plurality of additional shapes are separated from the plurality of shapes by one or more non-zero distances. A second data preparation process is performed using the data preparation element, after performing the first data preparation process. The second data preparation process modifies the plurality of additional shapes.

公开(公告)号：US10833061B2

公开(公告)日：2020-11-10

申请号：US16216843

申请日：2018-12-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Charles Chew-Yuen Young ,  Chih-Liang Chen ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng ,  Shun-Li Chen ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Chun-Kuang Chen ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/485 ,  G06F30/394 ,  H01L29/66 ,  H01L21/84

Abstract: Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure are arranged. At least one local interconnect over the non-active region and between two of the gate structures is selectively arranged, to couple at least one of contacts that is arranged above the first active region to at least one of the contacts that is arranged above the second active region.

公开(公告)号：US10796055B2

公开(公告)日：2020-10-06

申请号：US16660506

申请日：2019-10-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ping Chiang ,  Ming-Hui Chih ,  Chih-Wei Hsu ,  Ping-Chieh Wu ,  Ya-Ting Chang ,  Tsung-Yu Wang ,  Wen-Li Cheng ,  Hui En Yin ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau

IPC: G06F30/39 ,  G03F1/70 ,  G03F7/20

Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.