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公开(公告)号：US20150145002A1
公开(公告)日：2015-05-28
申请号：US14087425
申请日：2013-11-22
IPC分类号： H01L27/092 , H01L29/165 , H01L29/04 , H01L21/306 , H01L21/8238 , H01L21/762 , H01L21/02 , H01L29/161 , H01L29/06
CPC分类号： H01L21/823878 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/02532 , H01L21/0262 , H01L21/30604 , H01L21/30608 , H01L21/3065 , H01L21/3085 , H01L21/31 , H01L21/32 , H01L21/76224 , H01L21/823807 , H01L27/0922 , H01L29/0653 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66575
摘要： A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a (551) surface plane of the second semiconductor layer.
摘要翻译： 一种器件包括第一半导体层和第一半导体层上的第二半导体层。 第一半导体层和第二半导体层包括不同的材料。 半导体区域覆盖并接触第二半导体层，其中半导体区域的底表面接触第二半导体层的第一顶表面。 半导体区域和第二半导体层包括不同的材料。 半导体区域的底表面具有接触第二半导体层的（551）表面的倾斜部分。
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公开(公告)号：US10510868B2
公开(公告)日：2019-12-17
申请号：US16511580
申请日：2019-07-15
发明人： Yi-Jing Lee , Ming-Hua Yu
摘要： A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
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公开(公告)号：US20190371677A1
公开(公告)日：2019-12-05
申请号：US16390681
申请日：2019-04-22
发明人： Yi-Jing Lee , Tsung-Hsi Yang , Ming-Hua Yu
IPC分类号： H01L21/8238 , H01L27/092
摘要： An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.
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公开(公告)号：US10355105B2
公开(公告)日：2019-07-16
申请号：US15799344
申请日：2017-10-31
发明人： Yi-Jing Lee , Ming-Hua Yu
摘要： A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
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公开(公告)号：US20190131434A1
公开(公告)日：2019-05-02
申请号：US15799344
申请日：2017-10-31
发明人： Yi-Jing Lee , Ming-Hua Yu
CPC分类号： H01L29/66636 , H01L29/0847 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/66795 , H01L29/7851
摘要： A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.
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公开(公告)号：US10164022B2
公开(公告)日：2018-12-25
申请号：US15688214
申请日：2017-08-28
发明人： Yi-Jing Lee , Chi-Wen Liu
IPC分类号： H01L29/161 , H01L29/66 , H01L29/78 , H01L29/417 , H01L21/308 , H01L27/088 , H01L29/165 , H01L21/8234 , H01L29/778 , H01L29/06 , H01L29/10 , H01L21/02 , H01L21/3105 , H01L21/762 , H01L29/08 , H01L29/15 , H01L29/43
摘要： A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.
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公开(公告)号：US10084069B2
公开(公告)日：2018-09-25
申请号：US15647820
申请日：2017-07-12
发明人： Yi-Jing Lee , You-Ru Lin , Cheng-Tien Wan , Cheng-Hsien Wu , Chih-Hsin Ko
IPC分类号： H01L29/66 , H01L21/762 , H01L29/78 , H01L21/3065 , H01L21/02 , H01L21/306 , H01L27/088
CPC分类号： H01L29/66795 , H01L21/02532 , H01L21/0262 , H01L21/02631 , H01L21/02634 , H01L21/30625 , H01L21/3065 , H01L21/76224 , H01L27/0886 , H01L29/7853
摘要： A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
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公开(公告)号：US09922828B2
公开(公告)日：2018-03-20
申请号：US15411900
申请日：2017-01-20
发明人： Yi-Jing Lee , You-Ru Lin , Cheng-Tien Wan , Cheng-Hsien Wu , Chih-Hsin Ko
IPC分类号： H01L21/02 , H01L21/306 , H01L21/762 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/161
CPC分类号： H01L21/02694 , H01L21/02532 , H01L21/30625 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/0653 , H01L29/161 , H01L29/66795 , H01L29/7853
摘要： A method comprises performing a surface treatment on a plurality of recesses in a substrate to form a first cloak-shaped recess, a second cloak-shaped recess and a third cloak-shaped recess, wherein each cloak-shaped recess is between two isolation regions over the substrate and growing a semiconductor material in the first cloak-shaped recess, the second cloak-shaped recess and the third cloak-shaped recess to form a first cloak-shaped active region, a second cloak-shaped active region and a third cloak-shaped active region, wherein the first cloak-shaped active region has a first non-planar top surface, the second cloak-shaped active region has a second non-planar top surface and the third cloak-shaped active region has a third non-planar top surface.
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公开(公告)号：US09859380B2
公开(公告)日：2018-01-02
申请号：US15450201
申请日：2017-03-06
IPC分类号： H01L29/161 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/165 , H01L21/8234 , H01L21/762 , H01L21/3105 , H01L21/02 , H01L29/778 , H01L29/66
CPC分类号： H01L29/161 , H01L21/02532 , H01L21/0257 , H01L21/308 , H01L21/3081 , H01L21/31051 , H01L21/31055 , H01L21/76224 , H01L21/823412 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/0847 , H01L29/1054 , H01L29/1095 , H01L29/157 , H01L29/165 , H01L29/41791 , H01L29/432 , H01L29/66431 , H01L29/66712 , H01L29/66787 , H01L29/66795 , H01L29/778 , H01L29/7787 , H01L29/7789 , H01L29/7802 , H01L29/7842 , H01L29/7848 , H01L29/7849 , H01L29/785 , H01L29/7851
摘要： A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
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公开(公告)号：US20170125307A1
公开(公告)日：2017-05-04
申请号：US15404937
申请日：2017-01-12
IPC分类号： H01L21/8238 , H01L29/78
CPC分类号： H01L21/823878 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/1054 , H01L29/7854
摘要： A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.
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