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184 条记录 (耗时 0.036 秒)

    Non-volatile semiconductor memory device
    62.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4774556A

    公开(公告)日：1988-09-27

    申请号：US887625

    申请日：1986-07-21

    申请人： Tetsuo Fujii ,  Nobuyoshi Sakakibara ,  Toshio Sakakibara ,  Hiroshi Iwasaki

    发明人： Tetsuo Fujii ,  Nobuyoshi Sakakibara ,  Toshio Sakakibara ,  Hiroshi Iwasaki

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78 ,  H01L29/86

    CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L27/115 ,  H01L29/4236

    摘要： A non-volatile semiconductor memory device comprises a semiconductor substrate of a first conduction type, an impurity buried layer of a second conduction type formed at the surface of the semiconductor substrate for constituting either one of a drain region or a source region, an epitaxial layer of a second conduction type formed at the surface of said impurity buried layer, an insulatiang partition wall extended vertically from the surface of the epitaxial layer surrounding operation regions in the impurity buried layer for defining the operation regions therein, at least one electron holding portion extended vertically with a predetermined distance from the operation regions and disposed within the insulating partition wall apart from the operation region, the impurity buried layer or the drain region by an insulation film of such a thickness as causing a tunnel effect, control gates disposed within the insulation partition wall disposed on every electron holding portions on the side opposite to the operation regions and extended vertically with a certain gap from the electron maintaining portions, and a control gate disposed within the insulating partition wall on every electron holding portions on the opposite side to the operation region extended vertically and with a certain gap to the electron holding portions, and an impurity region of a second conduction type formed at the surface of the operation region for constituting the other of the drain region or the source region.

    摘要翻译： 非易失性半导体存储器件包括：第一导电类型的半导体衬底，形成在半导体衬底的表面的第二导电类型的杂质掩埋层，用于构成漏极区域或源极区域中的任一个，外延层 形成在所述杂质掩埋层的表面上的第二导电类型的绝缘分隔壁，包围在所述杂质掩埋层中的围绕所述杂质掩埋层的操作区域的外延层的表面垂直延伸的绝缘隔壁，用于限定其中的操作区域，至少一个电子保持部分延伸 垂直于操作区域预定的距离并且设置在与操作区域隔离的绝缘分隔壁内，通过具有隧道效应的厚度的绝缘膜的杂质掩埋层或漏极区域，设置在绝缘体内的控制栅极 分隔壁设置在侧面上的每个电子保持部分上 e与操作区域相对并且与电子维持部分具有一定间隙垂直延伸;以及控制栅极，设置在绝缘分隔壁内的每个电子保持部分上，与操作区域相对的一侧垂直延伸并且具有一定间隙 电子保持部分和形成在用于构成漏极区域或源极区域中的另一个的操作区域的表面处的第二导电类型的杂质区域。

    Method for manufacturing a semiconductor integrated device including bipolar and CMOS transistors
    63.
    发明授权
    Method for manufacturing a semiconductor integrated device including bipolar and CMOS transistors 失效
    用于制造包括双极和CMOS晶体管的半导体集成器件的方法

    公开(公告)号：US4694562A

    公开(公告)日：1987-09-22

    申请号：US925266

    申请日：1986-10-31

    申请人： Hiroshi Iwasaki ,  Shintaro Ito

    发明人： Hiroshi Iwasaki ,  Shintaro Ito

    IPC分类号： H01L21/8249 ,  H01L21/38

    CPC分类号： H01L21/8249

    摘要： A semiconductor integrated device (CBi-CMOS) is disclosed wherein both CMOS transistors and a vertical npn and pnp transistor are formed in a single semiconductor substrate and a latch up phenomenon in the CMOS is prevented. A method of manufacturing the CBi-CMOS is also disclosed. In the CBi-CMOS, four elements, that is, an n-MOSFET, a p-MOSFET and npn and pnp vertical transistors are formed in an n-type epitaxial silicon layer formed on a p-type silicon substrate. The n-MOSFET is formed in a p-well which has a p.sup.+ -type buried region. In the element region of the p-MOSFET, an n.sup.+ -type buried region is also formed. In the element regions of the npn and pnp vertical transistors, a first p.sup.+ -type isolation diffusion region is selectively formed. And an n.sup.+ -type buried region is selectively formed both in these element region of the npn and pnp vertical transistors. In the element region of the npn transistor, the vertical npn transistor is formed using the n-type region surrounded by the first p.sup.+ -type isolation diffusion region as a collector. In the element region of the pnp transistor, a p.sup.+ -type buried region is formed on the n.sup.+ -type buried region, and the vertical pnp transistor is formed using the p.sup.+ -type buried region as a collector. In this case, a second p.sup.+ -type isolation diffusion region is formed to isolate an n-type base region of the vertical pnp transistor.

    摘要翻译： 公开了一种半导体集成器件（CBi-CMOS），其中在单个半导体衬底中形成CMOS晶体管和垂直npn和pnp晶体管，并且防止了CMOS中的闭锁现象。 还公开了制造CBi-CMOS的方法。 在CBi-CMOS中，在p型硅衬底上形成的n型外延硅层中形成四个元件，即n-MOSFET，p-MOSFET和npn和pnp垂直晶体管。 n-MOSFET形成在具有p +型掩埋区的p阱中。 在p-MOSFET的元件区域中，也形成n +型掩埋区域。 在npn和pnp垂直晶体管的元件区域中，选择性地形成第一p +型隔离扩散区域。 并且在npn和pnp垂直晶体管的这些元件区域中选择性地形成n +型掩埋区域。 在npn晶体管的元件区域中，使用由第一p +型隔离扩散区域包围的n型区域作为集电极形成垂直npn晶体管。 在pnp晶体管的元件区域中，在n +型掩埋区域上形成p +型掩埋区域，使用p +型掩埋区域作为集电体形成垂直pnp晶体管。 在这种情况下，形成第二p +型隔离扩散区，以隔离垂直pnp晶体管的n型基极区。

    Preparation of aqueous medium suitable for preparing microcapsules
    64.
    发明授权
    Preparation of aqueous medium suitable for preparing microcapsules 失效
    适用于制备微胶囊的水性介质的制备

    公开(公告)号：US4349454A

    公开(公告)日：1982-09-14

    申请号：US115915

    申请日：1980-01-28

    申请人： Hiroshi Iwasaki ,  Shinsuke Irii ,  Mitsuru Kondo

    发明人： Hiroshi Iwasaki ,  Shinsuke Irii ,  Mitsuru Kondo

    IPC分类号： B41M5/136 ,  B41M5/165 ,  C09B11/02 ,  B01J13/00 ,  B01J13/02

    CPC分类号： C09B11/02 ,  B41M5/136 ,  B41M5/1655 ,  Y10S428/914

    摘要： A hydrophobic organic solvent containing a compound of the formula ##STR1## is dispersed and emulsified in an aqueous medium containing a sulfinic acid of the formulaR.sub.5 --SO.sub.2 H (I)and serving as an aqueous medium for preparing microcapsules to react the compounds of the formulae (I) and (II) and synthesize a diarylmethane derivative of the formula ##STR2## while encapsulating oily droplets of the resulting hydrophobic organic solvent solution of the diarylmethane derivative. Colorless chromogenic materials can be synthesized and encapsulated at the same time by this process.

    摘要翻译： 将含有式（II）化合物的疏水性有机溶剂分散并乳化在含有式R 5 -SO 2 H（I）的亚磺酸的水性介质中，并用作制备微胶囊以使化合物 的式（I）和（II）的化合物，并合成式（III）的二芳基甲烷衍生物，同时包封所得的二芳基甲烷衍生物的疏水性有机溶剂溶液的油滴。 无色发色材料可以通过该方法同时合成和包封。

    Process for preparation of peroxides
    65.
    发明授权
    Process for preparation of peroxides 失效
    过氧化物的制备方法

    公开(公告)号：US4266081A

    公开(公告)日：1981-05-05

    申请号：US944271

    申请日：1978-09-21

    申请人： Kenichi Mizuno ,  Hiroshi Iwasaki ,  Hirohiko Nambu

    发明人： Kenichi Mizuno ,  Hiroshi Iwasaki ,  Hirohiko Nambu

    IPC分类号： C07B61/00 ,  B01J27/00 ,  C07C67/00 ,  C07C407/00 ,  C07C409/16 ,  C07C179/093 ,  C07C179/06

    CPC分类号： C07C409/16 ,  C07C407/00 ,  C07C407/003

    摘要： A process for the preparation of peroxides by condensation reaction of a tertiary organic hydroperoxide with a tertiary alcohol, which is characterized in that zinc chloride is present as a catalyst in an amount of at least 1% by weight based on the tertiary alcohol, is disclosed. This process can be advantageously applied to continuous manufacture of peroxides, and according to this process, peroxides can be obtained in high yields.

    摘要翻译： 公开了通过叔有机氢过氧化物与叔醇的缩合反应来制备过氧化物的方法，其特征在于氯化锌作为催化剂以基于叔醇为至少1重量％的量存在。 。 该方法可以有利地应用于过氧化物的连续制造，并且根据该方法，可以高产率获得过氧化物。

    Heat-sensitive recording material
    67.
    发明授权
    Heat-sensitive recording material 失效
    热敏记录材料

    公开(公告)号：US4226912A

    公开(公告)日：1980-10-07

    申请号：US9083

    申请日：1979-02-02

    申请人： Hiroshi Iwasaki ,  Takeshi Murakami ,  Mitsuru Kondo

    发明人： Hiroshi Iwasaki ,  Takeshi Murakami ,  Mitsuru Kondo

    IPC分类号： B41M5/327 ,  B41M5/18

    CPC分类号： B41M5/3275 ,  Y10S428/913 ,  Y10S428/914

    摘要： The black color developing heat-sensitive recording material comprises a base sheet and a color developing layer formed on at least one surface of the base sheet, the color developing layer including colorless or light-colored chromogenic material and acceptor which is reactive with said chromogenic material to develop a black color. At least 60% by weight of the chromogenic material comprises at least two kinds of black color developing fluoran compounds having the eneral formula ##STR1## wherein R.sub.1, R.sub.2, R.sub.3, R.sub.4, R.sub.5, R.sub.6, X.sub.l and Ym are described hereinafter and the amount of each of said black color developing fluoran compounds is not larger than 90% by weight of the total amount of said black color developing fluoran compounds.

    摘要翻译： 黑色显影热敏记录材料包括基片和形成在基片的至少一个表面上的彩色显影层，彩色显影层包括无色或浅色显色材料和与所述显色材料反应的受体 开发黑色。 至少60重量％的显色材料包含至少两种具有下式的R 1，R 2，R 3，R 4，R 5，R 6，X 1和Y m的具有下式的R 1，R 2，R 3，R 4，R 5，R 6，X 1和Y m的具有下式的黑色显色荧烷化合物， 的所述黑色显影性荧烷化合物的比例不大于所述黑色显影性荧烷化合物总量的90重量％。

    Inflatable protector bag or vehicle safety device
    68.
    发明授权
    Inflatable protector bag or vehicle safety device 失效
    充气保护袋或车辆安全装置

    公开(公告)号：US4003588A

    公开(公告)日：1977-01-18

    申请号：US590496

    申请日：1975-06-26

    申请人： Takashi Oka ,  Syuichi Suzuki ,  Hilokazu Mitsuhashi ,  Hiroshi Iwasaki

    发明人： Takashi Oka ,  Syuichi Suzuki ,  Hilokazu Mitsuhashi ,  Hiroshi Iwasaki

    IPC分类号： B60R21/16 ,  B60R21/23 ,  B60R21/231 ,  B60R21/08

    CPC分类号： B60R21/231

    摘要： An inflatable protector bag of a vehicle safety device for protecting a vehicle occupant during a collision by the vehicle. The protective bag has a collapsed inoperative condition and an expanded operative condition having when unloaded, a generally hexahedral configuration consisting of two rectangular sheet sections, two isosceles triangular sheet sections and two congruent scalene quadrilateral sheet sections. The protector bag is produced from a totally closed hollow rectangular confinement having a pair of flat coextensively overlapping sheet sections such that three triangular pocket portions are formed at three of the vertices of the rectangular confinement and are sealed along the respective bases of the triangular pocket portions.

    摘要翻译： 一种用于在车辆碰撞期间保护车辆乘员的车辆安全装置的充气保护袋。 保护袋具有折叠的不工作状态和扩大的操作条件，当卸载时，由两个矩形片段，两个等腰三角形片段和两个一致的斜角四边形片段组成的大体六面体构造。 保护袋由完全封闭的中空矩形限制制成，其具有一对平坦的共同重叠的片段，使得在矩形限制的三个顶点处形成三个三角形凹坑部分，并沿着三角形袋部分的相应底部被密封 。

    Accessible electronic storage apparatus
    70.
    发明授权
    Accessible electronic storage apparatus 有权
    无障碍电子存储设备

    公开(公告)号：US07489027B2

    公开(公告)日：2009-02-10

    申请号：US12007034

    申请日：2008-01-04

    申请人： Hiroshi Iwasaki

    发明人： Hiroshi Iwasaki

    IPC分类号： H01L23/02 ,  H01L23/48

    CPC分类号： G06K19/07739 ,  G06K19/07743 ,  H01L23/3121 ,  H01L23/49855 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

    摘要： A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a. In addition, the storage apparatus 10 can be combined with a card type supporting means 21 that supports detachably with the flat type external connection terminal 12a exposed to one of the surfaces so as to be used as a card type storage apparatus 20 having bigger size.

    摘要翻译： 公开了一种存储装置10，其包括具有第一表面和第二表面的布线基板11，布置在布线基板11的第一表面上的平面型外部连接端子12a，设置在布线基板11的第二表面上的半导体装置14 布线基板11并具有连接到扁平型外部连接端子12a的连接端子14a，用于在布线基板11的第二表面上涂覆半导体器件14的模制树脂15，具有凹部的卡式支撑框架10a 或配线基板11，半导体装置14以及模塑树脂15的孔部，使平面型外部连接端子12a暴露于布线基板11的第一面，粘合树脂a一体地粘接 扁平型外部连接端子12a，布线基板11，半导体装置14，成型树脂15，以及支持f型卡 ame ame ame ame 此外，存储装置10可以与能够与暴露于其中一个表面的平面型外部连接端子12a可拆卸地支撑的卡式支撑装置21组合，以用作具有较大尺寸的卡式存储装置20。