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公开(公告)号:US20210111334A1
公开(公告)日:2021-04-15
申请号:US17131767
申请日:2020-12-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , JUN XIE
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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公开(公告)号:US20210020828A1
公开(公告)日:2021-01-21
申请号:US16531129
申请日:2019-08-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , JUN XIE
Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
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公开(公告)号:US10892194B2
公开(公告)日:2021-01-12
申请号:US16914483
申请日:2020-06-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Fu-Jung Chuang , Ching-Ling Lin , Po-Jen Chuang , Yu-Ren Wang , Wen-An Liang , Chia-Ming Kuo , Guan-Wei Huang , Yuan-Yu Chung , I-Ming Tseng
IPC: H01L21/00 , H01L21/8238 , H01L27/092 , H01L21/762
Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate having a n-type work function metal layer or a p-type work function metal layer.
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公开(公告)号:US20200373478A1
公开(公告)日:2020-11-26
申请号:US16438480
申请日:2019-06-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Chen-Yi Weng , Yi-Wei Tseng , Chin-Yang Hsieh , Jing-Yin Jhang , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , I-Ming Tseng , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
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公开(公告)号:US20200176331A1
公开(公告)日:2020-06-04
申请号:US16782083
申请日:2020-02-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Fu-Jung Chuang , Ching-Ling Lin , Po-Jen Chuang , Yu-Ren Wang , Wen-An Liang , Chia-Ming Kuo , Guan-Wei Huang , Yuan-Yu Chung , I-Ming Tseng
IPC: H01L21/8238 , H01L27/092 , H01L21/762
Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the fin-shaped structure into a first portion and a second portion, and a gate structure on the SDB structure. Preferably, the SDB structure includes silicon oxycarbonitride (SiOCN), a concentration portion of oxygen in SiOCN is between 30% to 60%, and the gate structure includes a metal gate.
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公开(公告)号:US10090398B2
公开(公告)日:2018-10-02
申请号:US15648439
申请日:2017-07-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Rai-Min Huang , I-Ming Tseng , Tong-Jyun Huang , Kuan-Hsien Li
IPC: H01L29/66 , H01L29/40 , H01L21/308 , H01L27/088 , H01L29/06 , H01L21/8234 , H01L29/78
Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.
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公开(公告)号:US20170309727A1
公开(公告)日:2017-10-26
申请号:US15648439
申请日:2017-07-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Rai-Min Huang , I-Ming Tseng , Tong-Jyun Huang , Kuan-Hsien Li
IPC: H01L29/66 , H01L29/40 , H01L27/088 , H01L29/06 , H01L21/308 , H01L21/8234
CPC classification number: H01L29/66545 , H01L21/3086 , H01L21/823437 , H01L27/088 , H01L29/0649 , H01L29/401 , H01L29/6656 , H01L29/785
Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.
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公开(公告)号:US09653402B2
公开(公告)日:2017-05-16
申请号:US14844004
申请日:2015-09-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: I-Ming Tseng , Wen-An Liang , Chen-Ming Huang
IPC: H01L29/76 , H01L29/94 , H01L23/535 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/161 , H01L29/16
CPC classification number: H01L21/823475 , H01L21/76805 , H01L21/76895 , H01L21/823431 , H01L21/823481 , H01L23/485 , H01L23/535 , H01L27/0886 , H01L29/0649 , H01L29/0653 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66515 , H01L29/66545 , H01L29/6681 , H01L29/7851
Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level.
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公开(公告)号:US20160293491A1
公开(公告)日:2016-10-06
申请号:US14696494
申请日:2015-04-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Tong-Jyun Huang , Rai-Min Huang , I-Ming Tseng , Kuan-Hsien Li , Chen-Ming Huang
IPC: H01L21/8234 , H01L29/06 , H01L27/088 , H01L21/308 , H01L21/02
CPC classification number: H01L21/76224 , H01L21/02271 , H01L21/3065 , H01L21/308 , H01L21/3081 , H01L21/3083 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/0653
Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
Abstract translation: 翅片结构切割过程包括以下步骤。 四个翅片结构形成在基板中,其中包括第一翅片结构,第二翅片结构,第三翅片结构和第四翅片结构的四个翅片结构彼此顺序并联。 执行第一鳍结构切割处理以去除第二鳍结构和第三鳍结构的顶部部分,从而由第二鳍结构形成第一凸起,以及由第三鳍结构形成的第二凸起。 执行第二鳍结构切割处理以完全去除第二凸起和第四鳍结构,但是将第一凸起保持在第一鳍结构旁边。 此外,本发明提供了一种通过所述方法形成的翅片结构。
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公开(公告)号:US09147612B2
公开(公告)日:2015-09-29
申请号:US14088445
申请日:2013-11-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Po-Cheng Huang , I-Ming Tseng , Yu-Ting Li , Chun-Hsiung Wang , Wu-Sian Sie , Yi-Liang Liu , Chia-Lin Hsu , Po-Chao Tsao , Chien-Ting Lin , Shih-Fang Tzou
IPC: H01L21/338 , H01L21/8234 , H01L21/265
CPC classification number: H01L21/823431 , H01L21/265 , H01L21/3086 , H01L29/6681
Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.
Abstract translation: 本发明提供一种用于形成半导体结构的制造方法,其中首先设置基板,在基板上设置硬掩模,然后将硬掩模图案化以形成多个散热片硬掩模和多个虚拟 翅片硬掩模,然后进行图案转印处理,将翅片硬掩模和翅片硬掩模的图案转移到基板中,以形成多个翅片组和多个虚拟翅片。 每个假翅片设置在一个翅片组的端侧,并进行翅片切割处理,以去除每个假翅片。
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